From 35cf26699946e9ae92b5234012f755062307445b Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Tue, 23 Jun 2026 23:55:30 -0700 Subject: [PATCH 01/23] Make CAN passive --- edg/abstract_parts/TestPoint.py | 2 +- edg/electronics_interfaces/CanPort.py | 19 +++++++++---------- edg/parts/interface/CanTransceiver_Iso1050.py | 12 +----------- .../interface/CanTransceiver_Sn65hvd230.py | 11 +---------- 4 files changed, 12 insertions(+), 32 deletions(-) diff --git a/edg/abstract_parts/TestPoint.py b/edg/abstract_parts/TestPoint.py index f56a4bf37..00c232928 100644 --- a/edg/abstract_parts/TestPoint.py +++ b/edg/abstract_parts/TestPoint.py @@ -188,7 +188,7 @@ class CanDiffTestPoint(BaseTypedTestPoint[CanDiffLink]): def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) - self.io: CanDiffPort = self.Port(CanDiffPort(DigitalBidir.empty()), [InOut]) + self.io: CanDiffPort = self.Port(CanDiffPort(), [InOut]) @override def contents(self) -> None: diff --git a/edg/electronics_interfaces/CanPort.py b/edg/electronics_interfaces/CanPort.py index cacd44843..ac4232a45 100644 --- a/edg/electronics_interfaces/CanPort.py +++ b/edg/electronics_interfaces/CanPort.py @@ -4,6 +4,7 @@ from ..electronics_model import * from .DigitalPorts import DigitalSink, DigitalSource, DigitalBidir, DigitalBidirBridge +from ..electronics_model.PassivePort import PassiveBridge class CanLogicLink(Link): @@ -69,7 +70,7 @@ class CanDiffLink(Link): def __init__(self) -> None: super().__init__() - self.nodes = self.Port(Vector(CanDiffPort(DigitalBidir.empty()))) # TODO mark as required + self.nodes = self.Port(Vector(CanDiffPort.empty())) # TODO mark as required # TODO write custom top level digital constraints # TODO future: digital constraints through link inference @@ -86,18 +87,18 @@ class CanDiffBridge(PortBridge): def __init__(self) -> None: super().__init__() - self.outer_port = self.Port(CanDiffPort(DigitalBidir.empty())) - self.inner_link = self.Port(CanDiffPort(DigitalBidir.empty())) + self.outer_port = self.Port(CanDiffPort.empty()) + self.inner_link = self.Port(CanDiffPort.empty()) @override def contents(self) -> None: super().contents() - self.canh_bridge = self.Block(DigitalBidirBridge()) + self.canh_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.canh, self.canh_bridge.outer_port) self.connect(self.canh_bridge.inner_link, self.inner_link.canh) - self.canl_bridge = self.Block(DigitalBidirBridge()) + self.canl_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.canl, self.canl_bridge.outer_port) self.connect(self.canl_bridge.inner_link, self.inner_link.canl) @@ -106,9 +107,7 @@ class CanDiffPort(Port[CanDiffLink]): link_type = CanDiffLink bridge_type = CanDiffBridge - def __init__(self, model: Optional[DigitalBidir] = None) -> None: + def __init__(self) -> None: super().__init__() - if model is None: # ideal by default - model = DigitalBidir() - self.canh = self.Port(model) - self.canl = self.Port(model) + self.canh = self.Port(Passive()) + self.canl = self.Port(Passive()) diff --git a/edg/parts/interface/CanTransceiver_Iso1050.py b/edg/parts/interface/CanTransceiver_Iso1050.py index d3a5f3141..2472617c0 100644 --- a/edg/parts/interface/CanTransceiver_Iso1050.py +++ b/edg/parts/interface/CanTransceiver_Iso1050.py @@ -24,17 +24,7 @@ def __init__(self) -> None: ) ) - self.can = self.Port( - CanDiffPort( - DigitalBidir( - voltage_limits=(-7, 7) - * Volt, # TODO: need better model of differential pins where there can be a common-mode offset - voltage_out=(0.8, 4.5) * Volt, - current_draw=(-4, 4) * mAmp, - current_limits=(-70, 70) * mAmp, - ) - ) - ) + self.can = self.Port(CanDiffPort()) @override def contents(self) -> None: diff --git a/edg/parts/interface/CanTransceiver_Sn65hvd230.py b/edg/parts/interface/CanTransceiver_Sn65hvd230.py index a05bcddbf..c5afb76c7 100644 --- a/edg/parts/interface/CanTransceiver_Sn65hvd230.py +++ b/edg/parts/interface/CanTransceiver_Sn65hvd230.py @@ -22,16 +22,7 @@ def __init__(self) -> None: ) ) - self.can = self.Port( - CanDiffPort( - DigitalBidir( - voltage_limits=(-2.5, 7.5) * Volt, - voltage_out=(0.5 * Volt, self.vcc.link().voltage.lower()), - current_draw=(-30, 30) * uAmp, - current_limits=(-250, 250) * mAmp, - ) - ) - ) + self.can = self.Port(CanDiffPort()) @override def contents(self) -> None: From a0ed55d35e48db1d5930e1d951f500cdd3264510 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 00:10:50 -0700 Subject: [PATCH 02/23] cleanup deprecations --- edg/abstract_parts/IoController.py | 6 +++ edg/circuits/PowerConditioning.py | 62 ++++++++-------------- edg/electronics_interfaces/GroundDummy.py | 19 ++----- edg/electronics_interfaces/VoltageDummy.py | 35 ++++-------- edg/parts/analog/opamp/Ina219.py | 23 ++++---- edg/parts/connector/Connectors.py | 20 +++---- 6 files changed, 57 insertions(+), 108 deletions(-) diff --git a/edg/abstract_parts/IoController.py b/edg/abstract_parts/IoController.py index 0a4506349..291ffd4a9 100644 --- a/edg/abstract_parts/IoController.py +++ b/edg/abstract_parts/IoController.py @@ -1,3 +1,4 @@ +import warnings from itertools import chain from typing import List, Dict, Tuple, Type, Optional, Any, Union, Callable, Mapping, Iterable from typing_extensions import override @@ -63,6 +64,11 @@ def __getattr__(self, item: str) -> Any: from .IoControllerInterfaceMixins import IoControllerCan self._can_mixin = self.with_mixin(IoControllerCan()) + warnings.warn( + f"can is now a mixin, use .with_mixin(IoControllerCan()).can mixin instead", + DeprecationWarning, + stacklevel=2, + ) return self._can_mixin.can else: raise AttributeError( diff --git a/edg/circuits/PowerConditioning.py b/edg/circuits/PowerConditioning.py index a6179d94a..fb9be90cd 100644 --- a/edg/circuits/PowerConditioning.py +++ b/edg/circuits/PowerConditioning.py @@ -1,6 +1,6 @@ -import warnings -from typing import Optional, Any +from typing import Optional +from deprecated import deprecated from typing_extensions import override from ..abstract_parts import * @@ -80,25 +80,15 @@ def generate(self) -> None: self.connect(pwr_in.net, diode.anode) self.connect(self.pwr_out.net, diode.cathode) - def __getattr__(self, item: str) -> Any: - if item == "pwr_in1": - warnings.warn( - f"Use pwr_ins.request(...) instead.", - DeprecationWarning, - stacklevel=2, - ) - return self.pwr_ins.request("1") - elif item == "pwr_in2": - warnings.warn( - f"Use pwr_ins.request(...) instead.", - DeprecationWarning, - stacklevel=2, - ) - return self.pwr_ins.request("2") - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes + @property + @deprecated(f"replaced with pwr_ins.request(...)") + def pwr_in1(self) -> VoltageSink: + return self.pwr_ins.request("1") + + @property + @deprecated(f"replaced with pwr_ins.request(...)") + def pwr_in2(self) -> VoltageSink: + return self.pwr_ins.request("2") class PriorityPowerOr(PowerConditioner, KiCadSchematicBlock, Block): @@ -235,26 +225,6 @@ class PmosChargerReverseProtection(PowerConditioner, KiCadSchematicBlock, Block) More info at: https://www.edn.com/reverse-voltage-protection-for-battery-chargers/ """ - def __getattr__(self, item: str) -> Any: - if item == "chg_in": - warnings.warn( - f"Use pwr_out instead. pwr_out is sink-capable (bidirectional) and chg_in is unnecessary.", - DeprecationWarning, - stacklevel=2, - ) - return self.pwr_out - elif item == "chg_out": - warnings.warn( - f"Use pwr_in instead. pwr_in is source-capable (bidirectional) and chg_out is unnecessary.", - DeprecationWarning, - stacklevel=2, - ) - return self.pwr_in - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes - def __init__( self, r1_val: RangeLike = 100 * kOhm(tol=0.01), @@ -325,6 +295,16 @@ def contents(self) -> None: }, ) + @property + @deprecated(f"chg_in is deprecated and unified with sink-capable (bidirectional) pwr_out") + def chg_in(self) -> VoltageSource: + return self.pwr_out + + @property + @deprecated(f"chg_out is deprecated and unified with source-capable (bidirectional) pwr_in") + def chg_out(self) -> VoltageSink: + return self.pwr_in + class SoftPowerGate(PowerSwitch, KiCadSchematicBlock, Block): # migrate from the multimater """A high-side PFET power gate that has a button to power on, can be latched on by an external signal, diff --git a/edg/electronics_interfaces/GroundDummy.py b/edg/electronics_interfaces/GroundDummy.py index e55e68736..b1d870f0e 100644 --- a/edg/electronics_interfaces/GroundDummy.py +++ b/edg/electronics_interfaces/GroundDummy.py @@ -1,5 +1,4 @@ -import warnings -from typing import Any +from deprecated import deprecated from ..electronics_model import * from .DummyDevices import BaseDummyBlock @@ -11,15 +10,7 @@ def __init__(self) -> None: super().__init__() self.io: Ground = self.Port(Ground(), [Common, InOut]) - def __getattr__(self, item: str) -> Any: - if item == "gnd": - warnings.warn( - f"DummyGround.gnd is deprecated, use .io instead.", - DeprecationWarning, - stacklevel=2, - ) - return self.io - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes + @property + @deprecated(f"DummyGround.gnd is deprecated, use .io instead.") + def gnd(self) -> Ground: + return self.io diff --git a/edg/electronics_interfaces/VoltageDummy.py b/edg/electronics_interfaces/VoltageDummy.py index 3bead0901..d55150874 100644 --- a/edg/electronics_interfaces/VoltageDummy.py +++ b/edg/electronics_interfaces/VoltageDummy.py @@ -1,5 +1,4 @@ -import warnings -from typing import Any +from deprecated import deprecated from ..electronics_model import * from .DummyDevices import BaseDummyBlock @@ -30,18 +29,10 @@ def __init__( self.voltage_limits = self.Parameter(RangeExpr(self.io.link().voltage_limits)) self.reverse_voltage = self.Parameter(RangeExpr(self.io.link().reverse_voltage)) - def __getattr__(self, item: str) -> Any: - if item == "pwr": - warnings.warn( - f"DummyVoltageSource.pwr is deprecated, use .io instead.", - DeprecationWarning, - stacklevel=2, - ) - return self.io - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes + @property + @deprecated(f"DummyVoltageSource.pwr is deprecated, use .io instead.") + def pwr(self) -> VoltageSource: + return self.io class DummyVoltageSink(BaseDummyBlock[VoltageLink]): @@ -68,15 +59,7 @@ def __init__( self.voltage = self.Parameter(RangeExpr(self.io.link().voltage)) self.current_limits = self.Parameter(RangeExpr(self.io.link().current_limits)) - def __getattr__(self, item: str) -> Any: - if item == "pwr": - warnings.warn( - f"DummyVoltageSink.pwr is deprecated, use .io instead.", - DeprecationWarning, - stacklevel=2, - ) - return self.io - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes + @property + @deprecated(f"DummyVoltageSink.pwr is deprecated, use .io instead.") + def pwr(self) -> VoltageSink: + return self.io diff --git a/edg/parts/analog/opamp/Ina219.py b/edg/parts/analog/opamp/Ina219.py index e255248a1..86fa244ed 100644 --- a/edg/parts/analog/opamp/Ina219.py +++ b/edg/parts/analog/opamp/Ina219.py @@ -1,6 +1,4 @@ -import warnings -from typing import Any - +from deprecated import deprecated from typing_extensions import override from ....circuits import * @@ -112,13 +110,12 @@ def generate(self) -> None: self.connect(self.Rs.sense_in, self.ic.in_neg) self.connect(self.Rs.sense_out, self.ic.in_pos) - def __getattr__(self, item: str) -> Any: - if item == "sense_pos": - warnings.warn(f"Use sense_pwr_in instead.", DeprecationWarning, stacklevel=2) - return self.sense_pwr_in - elif item == "sense_neg": - warnings.warn(f"Use sense_pwr_out instead.", DeprecationWarning, stacklevel=2) - return self.sense_pwr_out - else: - # ideally we'd use super().__getattr__(...), but that's not defined in base classes - raise AttributeError(item) + @property + @deprecated(f"replaced with sense_pwr_in") + def sense_pos(self) -> VoltageSink: + return self.sense_pwr_in + + @property + @deprecated(f"replaced with sense_pwr_out") + def sense_neg(self) -> VoltageSource: + return self.sense_pwr_out diff --git a/edg/parts/connector/Connectors.py b/edg/parts/connector/Connectors.py index 62a1279c2..d97149533 100644 --- a/edg/parts/connector/Connectors.py +++ b/edg/parts/connector/Connectors.py @@ -1,6 +1,6 @@ -import warnings from typing import Any +from deprecated import deprecated from typing_extensions import override from ...circuits import * @@ -72,19 +72,6 @@ class LipoConnector(Connector, Battery): Connector type not specified, up to the user through a refinement.""" - def __getattr__(self, item: str) -> Any: - if item == "chg": - warnings.warn( - f"Use pwr instead. pwr is sink-capable (bidirectional) and chg is unnecessary.", - DeprecationWarning, - stacklevel=2, - ) - return self.pwr - else: - raise AttributeError( - item - ) # ideally we'd use super().__getattr__(...), but that's not defined in base classes - def __init__( self, voltage: RangeLike = (2.5, 4.2) * Volt, @@ -109,6 +96,11 @@ def __init__( self.assign(self.actual_capacity, (500, 600) * mAmp) # arbitrary + @property + @deprecated(f"chg is deprecated and unified with sink-capable (bidirectional) pwr") + def chg(self) -> VoltageSource: + return self.pwr + class QwiicTarget(Connector): """A Qwiic (https://www.sparkfun.com/qwiic) connector to a I2C target. From d9533f9fa9c3560a7772f9b07962c8fc0172fef7 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 00:12:38 -0700 Subject: [PATCH 03/23] API pruning --- edg/circuits/PowerConditioning.py | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/edg/circuits/PowerConditioning.py b/edg/circuits/PowerConditioning.py index fb9be90cd..ec63db165 100644 --- a/edg/circuits/PowerConditioning.py +++ b/edg/circuits/PowerConditioning.py @@ -11,7 +11,7 @@ class SingleDiodePowerMerge(PowerConditioner, Block): preferred if both are connected. """ - def __init__(self, voltage_drop: RangeLike, reverse_recovery_time: RangeLike = RangeExpr.ALL) -> None: + def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: super().__init__() self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr())) # high-priority source @@ -27,7 +27,6 @@ def __init__(self, voltage_drop: RangeLike, reverse_recovery_time: RangeLike = R reverse_voltage=(0, self.pwr_in.link().voltage.upper() - self.pwr_in_diode.link().voltage.lower()), current=self.pwr_out.link().current_drawn, voltage_drop=voltage_drop, - reverse_recovery_time=reverse_recovery_time, ) ) @@ -45,10 +44,9 @@ def __init__(self, voltage_drop: RangeLike, reverse_recovery_time: RangeLike = R class DiodePowerMerge(PowerConditioner, GeneratorBlock): """Diode power merge block for multiple voltage sources.""" - def __init__(self, voltage_drop: RangeLike, reverse_recovery_time: RangeLike = RangeExpr.ALL) -> None: + def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: super().__init__() self.voltage_drop = self.ArgParameter(voltage_drop) - self.reverse_recovery_time = self.ArgParameter(reverse_recovery_time) self.pwr_ins = self.Port(Vector(VoltageSink.empty())) self.pwr_out = self.Port(VoltageSource(voltage_out=RangeExpr())) @@ -74,7 +72,6 @@ def generate(self) -> None: reverse_voltage=(0, self.pwr_out.voltage_out.upper() - pwr_in.link().voltage.lower()), current=self.pwr_out.link().current_drawn, voltage_drop=self.voltage_drop, - reverse_recovery_time=self.reverse_recovery_time, ) ) self.connect(pwr_in.net, diode.anode) @@ -369,7 +366,6 @@ def contents(self) -> None: reverse_voltage=control_voltage, current=RangeExpr.ZERO, # effectively no current voltage_drop=self.diode_drop, - reverse_recovery_time=RangeExpr.ALL, ) ) @@ -378,7 +374,6 @@ def contents(self) -> None: reverse_voltage=control_voltage, current=RangeExpr.ZERO, # effectively no current voltage_drop=self.diode_drop, - reverse_recovery_time=RangeExpr.ALL, ) ) From 4edc48f51a85f72e3ea6b0b3119f860c7d920e8d Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 00:14:43 -0700 Subject: [PATCH 04/23] fix --- edg/abstract_parts/TestPoint.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/edg/abstract_parts/TestPoint.py b/edg/abstract_parts/TestPoint.py index 00c232928..c11ad9531 100644 --- a/edg/abstract_parts/TestPoint.py +++ b/edg/abstract_parts/TestPoint.py @@ -194,7 +194,7 @@ def __init__(self, *args: Any, **kwargs: Any) -> None: def contents(self) -> None: super().contents() name_prefix = (self.tp_name == "").then_else(self.io.link().name(), self.tp_name) - self.tp_canh = self.Block(DigitalTestPoint(name_prefix + ".canh")) - self.tp_canl = self.Block(DigitalTestPoint(name_prefix + ".canl")) + self.tp_canh = self.Block(TestPoint(name_prefix + ".canh")) + self.tp_canl = self.Block(TestPoint(name_prefix + ".canl")) self.connect(self.tp_canh.io, self.io.canh) self.connect(self.tp_canl.io, self.io.canl) From 4f55e2cde2fb8035fd6bb8fcc3d76a873ca498d6 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 00:26:48 -0700 Subject: [PATCH 05/23] wip --- edg/electronics_interfaces/test_bundle_netlist.py | 12 ++++++------ examples/test_datalogger.py | 4 +++- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/edg/electronics_interfaces/test_bundle_netlist.py b/edg/electronics_interfaces/test_bundle_netlist.py index e394185a6..0ac087c46 100644 --- a/edg/electronics_interfaces/test_bundle_netlist.py +++ b/edg/electronics_interfaces/test_bundle_netlist.py @@ -292,9 +292,9 @@ def test_can_netlist(self) -> None: "link.canh", [net_pin(["node1"], "1"), net_pin(["node2"], "1"), net_pin(["node3"], "1")], [ - TransformUtil.Path.empty().append_block("node1").append_port("port", "canh", "net"), - TransformUtil.Path.empty().append_block("node2").append_port("port", "canh", "net"), - TransformUtil.Path.empty().append_block("node3").append_port("port", "canh", "net"), + TransformUtil.Path.empty().append_block("node1").append_port("port", "canh"), + TransformUtil.Path.empty().append_block("node2").append_port("port", "canh"), + TransformUtil.Path.empty().append_block("node3").append_port("port", "canh"), ], ), net.nets, @@ -304,9 +304,9 @@ def test_can_netlist(self) -> None: "link.canl", [net_pin(["node1"], "2"), net_pin(["node2"], "2"), net_pin(["node3"], "2")], [ - TransformUtil.Path.empty().append_block("node1").append_port("port", "canl", "net"), - TransformUtil.Path.empty().append_block("node2").append_port("port", "canl", "net"), - TransformUtil.Path.empty().append_block("node3").append_port("port", "canl", "net"), + TransformUtil.Path.empty().append_block("node1").append_port("port", "canl"), + TransformUtil.Path.empty().append_block("node2").append_port("port", "canl"), + TransformUtil.Path.empty().append_block("node3").append_port("port", "canl"), ], ), net.nets, diff --git a/examples/test_datalogger.py b/examples/test_datalogger.py index 9680eb6b8..50b380174 100644 --- a/examples/test_datalogger.py +++ b/examples/test_datalogger.py @@ -184,7 +184,9 @@ def contents(self) -> None: # this uses the legacy / simple (non-mixin) USB and CAN IO style self.connect(self.mcu.usb.request(), self.usb_conn.usb) - (self.can,), _ = self.chain(self.mcu.can.request("can"), imp.Block(CalSolCanBlock())) + (self.can,), _ = self.chain( + self.mcu.with_mixin(IoControllerCan()).can.request("can"), imp.Block(CalSolCanBlock()) + ) # mcu_i2c = self.mcu.i2c.request() # no devices, ignored for now # self.i2c_pullup = imp.Block(I2cPullup()) From 0dbd31cb892fedf68f8347dedba38ebea3f56ce6 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:18:29 -0700 Subject: [PATCH 06/23] clean up cc port --- edg/electronics_interfaces/UsbPort.py | 8 +++----- edg/parts/connector/UsbPorts.py | 12 +++++++----- edg/parts/interface/UsbPd_Fusb302b.py | 2 +- edg/parts/microcontroller/Stm32g431.py | 6 +++--- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/edg/electronics_interfaces/UsbPort.py b/edg/electronics_interfaces/UsbPort.py index e8db57126..7bbcec153 100644 --- a/edg/electronics_interfaces/UsbPort.py +++ b/edg/electronics_interfaces/UsbPort.py @@ -111,8 +111,6 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() # TODO perhaps enable crossover connections as optional layout optimization? - # TODO check both b and pull aren't simultaneously connected? - # TODO write protocol-level signal constraints? self.cc1 = self.connect(self.a.cc1, self.b.cc1) self.cc2 = self.connect(self.a.cc2, self.b.cc2) @@ -120,7 +118,7 @@ def contents(self) -> None: class UsbCcPort(Port[UsbCcLink]): link_type = UsbCcLink - def __init__(self, pullup_capable: BoolLike = False) -> None: + def __init__(self) -> None: super().__init__() - self.cc1 = self.Port(DigitalBidir(pullup_capable=pullup_capable)) - self.cc2 = self.Port(DigitalBidir(pullup_capable=pullup_capable)) + self.cc1 = self.Port(Passive()) + self.cc2 = self.Port(Passive()) diff --git a/edg/parts/connector/UsbPorts.py b/edg/parts/connector/UsbPorts.py index 406de4591..27fc50c65 100644 --- a/edg/parts/connector/UsbPorts.py +++ b/edg/parts/connector/UsbPorts.py @@ -40,7 +40,6 @@ def __init__( self, voltage_out: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # allow custom PD voltage and current current_limits: RangeLike = UsbConnector.USB2_CURRENT_LIMITS, - cc_pullup_capable: BoolLike = False, ) -> None: super().__init__() self.pwr = self.Port(VoltageSource(voltage_out=voltage_out, current_limits=current_limits), optional=True) @@ -49,7 +48,7 @@ def __init__( self.usb = self.Port(UsbHostPort(), optional=True) self.shield = self.Port(Ground(), optional=True) - self.cc = self.Port(UsbCcPort(pullup_capable=cc_pullup_capable), optional=True) + self.cc = self.Port(UsbCcPort(), optional=True) @override def contents(self) -> None: @@ -183,9 +182,12 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - pdr_model = PulldownResistor(resistance=5.1 * kOhm(tol=0.01)) - self.cc1 = self.Block(pdr_model).connected(self.gnd, self.cc.cc1) - self.cc2 = self.Block(pdr_model).connected(self.gnd, self.cc.cc2) + pdr_model = Resistor(resistance=5.1 * kOhm(tol=0.01)) + self.cc1 = self.Block(pdr_model) + self.cc2 = self.Block(pdr_model) + self.connect(self.gnd.net, self.cc1.a, self.cc2.a) + self.connect(self.cc1.b, self.cc.cc1) + self.connect(self.cc2.b, self.cc.cc2) class Tpd2e009(UsbEsdDiode, FootprintBlock, JlcPart): diff --git a/edg/parts/interface/UsbPd_Fusb302b.py b/edg/parts/interface/UsbPd_Fusb302b.py index 84b9e33a5..c5675369c 100644 --- a/edg/parts/interface/UsbPd_Fusb302b.py +++ b/edg/parts/interface/UsbPd_Fusb302b.py @@ -16,7 +16,7 @@ def __init__(self) -> None: ) self.gnd = self.Port(Ground()) - self.cc = self.Port(UsbCcPort()) # TODO pass in port models? + self.cc = self.Port(UsbCcPort()) i2c_model = DigitalBidir( # interestingly, IO maximum voltages are not specified voltage_out=(0, 0.35) * Volt, # low-level output voltage current_limits=(-20, 0) * mAmp, # low-level output current limits diff --git a/edg/parts/microcontroller/Stm32g431.py b/edg/parts/microcontroller/Stm32g431.py index 7222f4848..3b491f73e 100644 --- a/edg/parts/microcontroller/Stm32g431.py +++ b/edg/parts/microcontroller/Stm32g431.py @@ -161,9 +161,9 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("PA15", {"PA15": dio_ftf_model}), PinResource("PB0", {"PB0": dio_tta_model, "ADC1_IN15": adc_model}), PinResource("PB3", {"PB3": dio_ft_model}), - PinResource("PB4", {"PB4": dio_ftc_model}), + PinResource("PB4", {"PB4": dio_ftc_model, "UCPD1_CC2": Passive()}), PinResource("PB5", {"PB5": dio_ftf_model}), - PinResource("PB6", {"PB6": dio_ftc_model}), + PinResource("PB6", {"PB6": dio_ftc_model, "UCPD1_CC1": Passive()}), PinResource("PB7", {"PB7": dio_ftf_model}), PinResource("PB8", {"PB8": dio_ftf_model}), # From table 13 @@ -217,7 +217,7 @@ def _io_pinmap(self) -> PinMapUtil: }, ), PeripheralFixedResource("USB", UsbDevicePort(DigitalBidir.empty()), {"dm": ["PA11"], "dp": ["PA12"]}), - PeripheralFixedResource("USBCC", UsbCcPort(pullup_capable=True), {"cc1": ["PB6"], "cc2": ["PB4"]}), + PeripheralFixedResource("USBCC", UsbCcPort(), {"cc1": ["PB6"], "cc2": ["PB4"]}), ] ).remap_pins(self._PIN_MAPPING) From 0c0a6c953e0535a69eab3384cc56111bfe787c9d Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:26:18 -0700 Subject: [PATCH 07/23] wip usb passive refactor --- edg/circuits/UsbBitBang.py | 11 +++++++--- edg/circuits/UsbSeriesResistor.py | 8 +++++-- edg/electronics_interfaces/UsbPort.py | 29 +++++++++++--------------- edg/parts/microcontroller/Stm32f103.py | 2 +- 4 files changed, 27 insertions(+), 23 deletions(-) diff --git a/edg/circuits/UsbBitBang.py b/edg/circuits/UsbBitBang.py index ffc2f5003..5f78aa7f0 100644 --- a/edg/circuits/UsbBitBang.py +++ b/edg/circuits/UsbBitBang.py @@ -47,9 +47,14 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() - self.dp_pull_res = self.Block(DigitalSeriesResistor(1.5 * kOhm(tol=0.05))).connected(self.dp_pull, self.usb.dp) - self.dp_res = self.Block(DigitalBidirSeriesResistor(68 * Ohm(tol=0.05))).connected(self.dp, self.usb.dp) - self.dm_res = self.Block(DigitalBidirSeriesResistor(68 * Ohm(tol=0.05))).connected(self.dm, self.usb.dm) + self.dp_pull_res = self.Block(Resistor(1.5 * kOhm(tol=0.05))) + self.connect(self.dp_pull_res.a, self.dp_pull.net) + self.dp_res = self.Block(Resistor(68 * Ohm(tol=0.05))) + self.connect(self.dp_res.a, self.dp.net) + self.connect(self.dp_pull_res.b, self.dp_res.b, self.usb.dp) + self.dm_res = self.Block(Resistor(68 * Ohm(tol=0.05))) + self.connect(self.dm_res.a, self.dm.net) + self.connect(self.dm_res.b, self.usb.dm) def connected_from(self, dp_pull: Port[DigitalLink], dp: Port[DigitalLink], dm: Port[DigitalLink]) -> "UsbBitBang": builder.block().connect(dp_pull, self.dp_pull) diff --git a/edg/circuits/UsbSeriesResistor.py b/edg/circuits/UsbSeriesResistor.py index 655c95bba..758bb028b 100644 --- a/edg/circuits/UsbSeriesResistor.py +++ b/edg/circuits/UsbSeriesResistor.py @@ -15,5 +15,9 @@ def __init__(self, resistance: RangeLike) -> None: @override def contents(self) -> None: super().contents() - self.dp = self.Block(DigitalBidirSeriesResistor(self.resistance)).connected(self.interior.dp, self.exterior.dp) - self.dm = self.Block(DigitalBidirSeriesResistor(self.resistance)).connected(self.interior.dm, self.exterior.dm) + self.dp = self.Block(Resistor(self.resistance)) + self.connect(self.dp.a, self.interior.dp) + self.connect(self.dp.b, self.exterior.dp) + self.dm = self.Block(Resistor(self.resistance)) + self.connect(self.dm.a, self.interior.dm) + self.connect(self.dm.b, self.exterior.dm) diff --git a/edg/electronics_interfaces/UsbPort.py b/edg/electronics_interfaces/UsbPort.py index 7bbcec153..93f73092f 100644 --- a/edg/electronics_interfaces/UsbPort.py +++ b/edg/electronics_interfaces/UsbPort.py @@ -4,6 +4,7 @@ from ..electronics_model import * from .DigitalPorts import DigitalBidir +from ..electronics_model.PassivePort import PassiveBridge class UsbLink(Link): @@ -34,15 +35,13 @@ def __init__(self) -> None: @override def contents(self) -> None: - from .DigitalPorts import DigitalBidirBridge - super().contents() - self.dm_bridge = self.Block(DigitalBidirBridge()) + self.dm_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.dm, self.dm_bridge.outer_port) self.connect(self.dm_bridge.inner_link, self.inner_link.dm) - self.dp_bridge = self.Block(DigitalBidirBridge()) + self.dp_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.dp, self.dp_bridge.outer_port) self.connect(self.dp_bridge.inner_link, self.inner_link.dp) @@ -53,8 +52,8 @@ class UsbHostPort(Port[UsbLink]): def __init__(self) -> None: super().__init__() - self.dp = self.Port(DigitalBidir()) - self.dm = self.Port(DigitalBidir()) + self.dp = self.Port(Passive()) + self.dm = self.Port(Passive()) class UsbDeviceBridge(PortBridge): @@ -65,15 +64,13 @@ def __init__(self) -> None: @override def contents(self) -> None: - from .DigitalPorts import DigitalBidirBridge - super().contents() - self.dm_bridge = self.Block(DigitalBidirBridge()) + self.dm_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.dm, self.dm_bridge.outer_port) self.connect(self.dm_bridge.inner_link, self.inner_link.dm) - self.dp_bridge = self.Block(DigitalBidirBridge()) + self.dp_bridge = self.Block(PassiveBridge()) self.connect(self.outer_port.dp, self.dp_bridge.outer_port) self.connect(self.dp_bridge.inner_link, self.inner_link.dp) @@ -82,12 +79,10 @@ class UsbDevicePort(Port[UsbLink]): link_type = UsbLink bridge_type = UsbDeviceBridge - def __init__(self, model: Optional[DigitalBidir] = None) -> None: + def __init__(self) -> None: super().__init__() - if model is None: - model = DigitalBidir() # ideal by default - self.dp = self.Port(model) - self.dm = self.Port(model) + self.dp = self.Port(Passive()) + self.dm = self.Port(Passive()) class UsbPassivePort(Port[UsbLink]): @@ -95,8 +90,8 @@ class UsbPassivePort(Port[UsbLink]): def __init__(self) -> None: super().__init__() - self.dp = self.Port(DigitalBidir()) - self.dm = self.Port(DigitalBidir()) + self.dp = self.Port(Passive()) + self.dm = self.Port(Passive()) class UsbCcLink(Link): diff --git a/edg/parts/microcontroller/Stm32f103.py b/edg/parts/microcontroller/Stm32f103.py index 288bcfff5..795f0d1c2 100644 --- a/edg/parts/microcontroller/Stm32f103.py +++ b/edg/parts/microcontroller/Stm32f103.py @@ -252,7 +252,7 @@ def __init__(self, resistance: RangeLike): self.dp = self.Block(Resistor(resistance)) self.connect(self.pwr.net, self.dp.a) - self.connect(self.usb.dp.net, self.dp.b) + self.connect(self.usb.dp, self.dp.b) class Stm32f103_48( From ec87898eb8e12051f9962f0b90127705a355eb90 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:31:30 -0700 Subject: [PATCH 08/23] one example builds --- edg/circuits/UsbBitBang.py | 7 ++++--- edg/circuits/UsbSeriesResistor.py | 4 ++-- edg/parts/connector/UsbPorts.py | 4 ++-- edg/parts/microcontroller/Ch32v203.py | 8 +++++--- 4 files changed, 13 insertions(+), 10 deletions(-) diff --git a/edg/circuits/UsbBitBang.py b/edg/circuits/UsbBitBang.py index 5f78aa7f0..ce1591a28 100644 --- a/edg/circuits/UsbBitBang.py +++ b/edg/circuits/UsbBitBang.py @@ -39,9 +39,10 @@ def __init__(self) -> None: # to propagate to the FPGA port, and this causes both to deadlock (both link voltages depend on # the port voltages, and neither is available until the other link voltage is available). # Other ideas include moving to a fixed point solver, but that has other trade-offs. - self.dp = self.Port(DigitalBidir.empty()) - self.dm = self.Port(DigitalBidir.empty()) - self.dp_pull = self.Port(DigitalSink.empty()) + # TODO: need modeling against USB spec + self.dp = self.Port(DigitalBidir()) + self.dm = self.Port(DigitalBidir()) + self.dp_pull = self.Port(DigitalSink()) @override def contents(self) -> None: diff --git a/edg/circuits/UsbSeriesResistor.py b/edg/circuits/UsbSeriesResistor.py index 758bb028b..8187e6879 100644 --- a/edg/circuits/UsbSeriesResistor.py +++ b/edg/circuits/UsbSeriesResistor.py @@ -9,8 +9,8 @@ class UsbSeriesResistor(InternalSubcircuit, Block): def __init__(self, resistance: RangeLike) -> None: super().__init__() self.resistance = self.ArgParameter(resistance) - self.interior = self.Port(UsbHostPort.empty(), [Input]) - self.exterior = self.Port(UsbDevicePort.empty(), [Output]) + self.interior = self.Port(UsbHostPort(), [Input]) + self.exterior = self.Port(UsbDevicePort(), [Output]) @override def contents(self) -> None: diff --git a/edg/parts/connector/UsbPorts.py b/edg/parts/connector/UsbPorts.py index 27fc50c65..201aa5277 100644 --- a/edg/parts/connector/UsbPorts.py +++ b/edg/parts/connector/UsbPorts.py @@ -176,8 +176,8 @@ class UsbCcPulldownResistor(InternalSubcircuit, Block): def __init__(self) -> None: super().__init__() - self.cc = self.Port(UsbCcPort.empty(), [Input]) - self.gnd = self.Port(Ground.empty(), [Common]) + self.cc = self.Port(UsbCcPort(), [Input]) + self.gnd = self.Port(Ground(), [Common]) @override def contents(self) -> None: diff --git a/edg/parts/microcontroller/Ch32v203.py b/edg/parts/microcontroller/Ch32v203.py index c0dfac526..a37041bf6 100644 --- a/edg/parts/microcontroller/Ch32v203.py +++ b/edg/parts/microcontroller/Ch32v203.py @@ -215,8 +215,10 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("PA8", {"PA8": self._dio_ft_model}), PinResource("PA9", {"PA9": self._dio_ft_model}), PinResource("PA10", {"PA10": self._dio_ft_model}), - PinResource("PA11", {"PA11": self._dio_ft_model}), - PinResource("PA12", {"PA12": self._dio_ft_model}), # merged w/ SWDIO on some devices + PinResource("PA11", {"PA11": self._dio_ft_model, "USB1DM": Passive()}), + PinResource( + "PA12", {"PA12": self._dio_ft_model, "USB1DP": Passive()} + ), # merged w/ SWDIO on some devices PinResource("PA13", {"PA13": self._dio_ft_model}), # SWDIO PinResource("PA14", {"PA14": self._dio_ft_model}), # SWCLK PinResource("PA15", {"PA15": self._dio_ft_model}), @@ -234,7 +236,7 @@ def _io_pinmap(self) -> PinMapUtil: # unavailable on K8 # PeripheralFixedResource("USART3", uart_model, {"tx": ["PB10"], "rx": ["PB11"]}), # PeripheralFixedResource("USART4", uart_model, {"tx": ["PB0", "PA5"], "rx": ["PB1", "PB5"]}), - PeripheralFixedResource("USB", UsbDevicePort(DigitalBidir.empty()), {"dm": ["PA11"], "dp": ["PA12"]}), + PeripheralFixedResource("USB", UsbDevicePort(), {"dm": ["PA11"], "dp": ["PA12"]}), # PeripheralFixedResource("USBFS", UsbDevicePort(DigitalBidir.empty()), {"dm": ["PB6"], "dp": ["PB7"]}), PeripheralFixedResource("I2C1", i2c_model, {"scl": ["PB6", "PB8"], "sda": ["PB7", "PB9"]}), PeripheralFixedResource("I2C1_T", i2c_target_model, {"scl": ["PB6", "PB8"], "sda": ["PB7", "PB9"]}), From 42814cfba2663ef60a60409ef9ed7085a67eee13 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:37:03 -0700 Subject: [PATCH 09/23] refactor mciros --- edg/parts/microcontroller/Esp32s3.py | 6 +++--- edg/parts/microcontroller/Rp2040.py | 12 +----------- edg/parts/microcontroller/Stm32f103.py | 6 +++--- edg/parts/microcontroller/Stm32g431.py | 6 +++--- edg/parts/microcontroller/Stm32l432.py | 4 ++-- 5 files changed, 12 insertions(+), 22 deletions(-) diff --git a/edg/parts/microcontroller/Esp32s3.py b/edg/parts/microcontroller/Esp32s3.py index a3d69b530..2ee8b29d3 100644 --- a/edg/parts/microcontroller/Esp32s3.py +++ b/edg/parts/microcontroller/Esp32s3.py @@ -169,8 +169,8 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("XTAL_32K_N", {"GPIO16": self._dio_model}), # also ADC2_CH5 PinResource("GPIO17", {"GPIO17": self._dio_model}), # also ADC2_CH6 PinResource("GPIO18", {"GPIO18": self._dio_model}), # also ADC2_CH7 - PinResource("GPIO19", {"GPIO19": self._dio_model}), # also ADC2_CH8 / USB_D- - PinResource("GPIO20", {"GPIO20": self._dio_model}), # also ADC2_CH9 / USB_D+ + PinResource("GPIO19", {"GPIO19": self._dio_model, "USB_D-": Passive()}), # also ADC2_CH8 + PinResource("GPIO20", {"GPIO20": self._dio_model, "USB_D+": Passive()}), # also ADC2_CH9 PinResource("GPIO21", {"GPIO21": self._dio_model}), # VDD_SPI domain # section 2.3.3, these are allocated for flash and should not be used @@ -220,7 +220,7 @@ def _io_pinmap(self) -> PinMapUtil: PeripheralAnyResource( "DVP", dvp8_model ), # TODO this also eats an I2S port, also available as 16-bit - PeripheralFixedResource("USB", UsbDevicePort.empty(), {"dp": ["GPIO20"], "dm": ["GPIO19"]}), + PeripheralFixedResource("USB", UsbDevicePort(), {"dp": ["GPIO20"], "dm": ["GPIO19"]}), ] ) .remap_pins(self._PIN_MAPPING) diff --git a/edg/parts/microcontroller/Rp2040.py b/edg/parts/microcontroller/Rp2040.py index c99b0239d..11c72dd9c 100644 --- a/edg/parts/microcontroller/Rp2040.py +++ b/edg/parts/microcontroller/Rp2040.py @@ -103,16 +103,6 @@ def __init__(self, **kwargs: Any) -> None: ) # Additional ports (on top of IoController) - self._dio_usb_model = self._dio_ft_model = self._dio_std_model = DigitalBidir.from_supply( # table 4.4 - self.gnd, - self.iovdd, - voltage_limit_tolerance=(-0.3, 0.3) * Volt, - current_limits=(-12, 12) * mAmp, # by IOH / IOL modes - input_threshold_abs=(0.8, 2.0) * Volt, # for IOVdd=3.3, TODO other IOVdd ranges - pullup_capable=True, - pulldown_capable=True, - ) - self.qspi = self.Port(SpiController(self._dio_std_model), optional=self._model) # TODO actually QSPI self.qspi_cs = self.Port(self._dio_std_model, optional=self._model) self.qspi_sd2 = self.Port(self._dio_std_model, optional=self._model) @@ -223,7 +213,7 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("GPIO28", {"GPIO28": self._dio_std_model, "ADC2": adc_model}), PinResource("GPIO29", {"GPIO29": self._dio_std_model, "ADC3": adc_model}), # fixed-pin peripherals - PeripheralFixedPin("USB", UsbDevicePort(self._dio_usb_model), {"dm": "USB_DM", "dp": "USB_DP"}), + PeripheralFixedPin("USB", UsbDevicePort(), {"dm": "USB_DM", "dp": "USB_DP"}), # reassignable peripherals PeripheralFixedResource( "UART0", diff --git a/edg/parts/microcontroller/Stm32f103.py b/edg/parts/microcontroller/Stm32f103.py index 795f0d1c2..752b775fa 100644 --- a/edg/parts/microcontroller/Stm32f103.py +++ b/edg/parts/microcontroller/Stm32f103.py @@ -172,8 +172,8 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("PA8", {"PA8": dio_ft_model}), PinResource("PA9", {"PA9": dio_ft_model}), PinResource("PA10", {"PA10": dio_ft_model}), - PinResource("PA11", {"PA11": dio_ft_model}), - PinResource("PA12", {"PA12": dio_ft_model}), + PinResource("PA11", {"PA11": dio_ft_model, "USBDM": Passive()}), + PinResource("PA12", {"PA12": dio_ft_model, "USBDP": Passive()}), # PinResource('PA13', {'PA13': dio_ft_model}), # forced SWDIO default is JTMS/SWDIO # PinResource('PA14', {'PA14': dio_ft_model}), # forced SWCLK, default is JTCK/SWCLK PinResource("PA15", {"PA15": dio_ft_model}), # default is JTDI @@ -209,7 +209,7 @@ def _io_pinmap(self) -> PinMapUtil: CanControllerPort(DigitalBidir.empty()), {"txd": ["PA12", "PD1", "PB9"], "rxd": ["PA11", "PD0", "PB8"]}, ), - PeripheralFixedResource("USB", UsbDevicePort(DigitalBidir.empty()), {"dm": ["PA11"], "dp": ["PA12"]}), + PeripheralFixedResource("USB", UsbDevicePort(), {"dm": ["PA11"], "dp": ["PA12"]}), PeripheralFixedPin( "SWD", SwdTargetPort(dio_std_model), diff --git a/edg/parts/microcontroller/Stm32g431.py b/edg/parts/microcontroller/Stm32g431.py index 3b491f73e..b6c40f229 100644 --- a/edg/parts/microcontroller/Stm32g431.py +++ b/edg/parts/microcontroller/Stm32g431.py @@ -154,8 +154,8 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("PA8", {"PA8": dio_ftf_model}), PinResource("PA9", {"PA9": dio_ftfd_model}), PinResource("PA10", {"PA10": dio_ftda_model}), - PinResource("PA11", {"PA11": dio_ftu_model}), # USB_DM - PinResource("PA12", {"PA12": dio_ftu_model}), # USB_DP + PinResource("PA11", {"PA11": dio_ftu_model, "USB_DM": Passive()}), + PinResource("PA12", {"PA12": dio_ftu_model, "USB_DP": Passive()}), PinResource("PA13", {"PA13": dio_ftf_model}), PinResource("PA14", {"PA14": dio_ftf_model}), PinResource("PA15", {"PA15": dio_ftf_model}), @@ -216,7 +216,7 @@ def _io_pinmap(self) -> PinMapUtil: "swclk": ["PA14"], }, ), - PeripheralFixedResource("USB", UsbDevicePort(DigitalBidir.empty()), {"dm": ["PA11"], "dp": ["PA12"]}), + PeripheralFixedResource("USB", UsbDevicePort(), {"dm": ["PA11"], "dp": ["PA12"]}), PeripheralFixedResource("USBCC", UsbCcPort(), {"cc1": ["PB6"], "cc2": ["PB4"]}), ] ).remap_pins(self._PIN_MAPPING) diff --git a/edg/parts/microcontroller/Stm32l432.py b/edg/parts/microcontroller/Stm32l432.py index 63f969900..a8ae437dc 100644 --- a/edg/parts/microcontroller/Stm32l432.py +++ b/edg/parts/microcontroller/Stm32l432.py @@ -145,8 +145,8 @@ def _io_pinmap(self) -> PinMapUtil: PinResource("PA8", {"PA8": dio_ft_model}), PinResource("PA9", {"PA8": dio_ftf_model}), PinResource("PA10", {"PA10": dio_ftf_model}), - PinResource("PA11", {"PA11": dio_ftu_model}), - PinResource("PA12", {"PA12": dio_ftu_model}), + PinResource("PA11", {"PA11": dio_ftu_model, "USB_DM": Passive()}), + PinResource("PA12", {"PA12": dio_ftu_model, "USB_DP": Passive()}), PinResource("PA13", {"PA13": dio_ft_model}), PinResource("PA14", {"PA14": dio_ft_model}), PinResource("PA15", {"PA15": dio_ft_model}), From 106fde778b7416511c9f7f3d23849a0818c3a4be Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:38:12 -0700 Subject: [PATCH 10/23] Update Rp2040.py --- edg/parts/microcontroller/Rp2040.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/edg/parts/microcontroller/Rp2040.py b/edg/parts/microcontroller/Rp2040.py index 11c72dd9c..8a4282a4b 100644 --- a/edg/parts/microcontroller/Rp2040.py +++ b/edg/parts/microcontroller/Rp2040.py @@ -103,6 +103,16 @@ def __init__(self, **kwargs: Any) -> None: ) # Additional ports (on top of IoController) + self._dio_ft_model = self._dio_std_model = DigitalBidir.from_supply( # table 4.4 + self.gnd, + self.iovdd, + voltage_limit_tolerance=(-0.3, 0.3) * Volt, + current_limits=(-12, 12) * mAmp, # by IOH / IOL modes + input_threshold_abs=(0.8, 2.0) * Volt, # for IOVdd=3.3, TODO other IOVdd ranges + pullup_capable=True, + pulldown_capable=True, + ) + self.qspi = self.Port(SpiController(self._dio_std_model), optional=self._model) # TODO actually QSPI self.qspi_cs = self.Port(self._dio_std_model, optional=self._model) self.qspi_sd2 = self.Port(self._dio_std_model, optional=self._model) From 2b3129939be47444dc1be723e59487d702b3d5fc Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 01:50:59 -0700 Subject: [PATCH 11/23] Update UsbSeriesResistor.py --- edg/circuits/UsbSeriesResistor.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/edg/circuits/UsbSeriesResistor.py b/edg/circuits/UsbSeriesResistor.py index 8187e6879..fa893b4e9 100644 --- a/edg/circuits/UsbSeriesResistor.py +++ b/edg/circuits/UsbSeriesResistor.py @@ -16,8 +16,8 @@ def __init__(self, resistance: RangeLike) -> None: def contents(self) -> None: super().contents() self.dp = self.Block(Resistor(self.resistance)) - self.connect(self.dp.a, self.interior.dp) - self.connect(self.dp.b, self.exterior.dp) + self.connect(self.dp.a, self.exterior.dp) + self.connect(self.dp.b, self.interior.dp) self.dm = self.Block(Resistor(self.resistance)) - self.connect(self.dm.a, self.interior.dm) - self.connect(self.dm.b, self.exterior.dm) + self.connect(self.dm.a, self.exterior.dm) + self.connect(self.dm.b, self.interior.dm) From b772ac15aa8f2f69481cb11e246cf25821cd3526 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 21:36:38 -0700 Subject: [PATCH 12/23] fix usb (and generally passive) pinning --- edg/abstract_parts/IoControllerWrapper.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/edg/abstract_parts/IoControllerWrapper.py b/edg/abstract_parts/IoControllerWrapper.py index d7bdcc196..6a8a453d6 100644 --- a/edg/abstract_parts/IoControllerWrapper.py +++ b/edg/abstract_parts/IoControllerWrapper.py @@ -100,7 +100,7 @@ def recurse_port(port: Port, prefix: str) -> None: def _remap_to_footprint_pinning( self, pin_assigns: Dict[str, Tuple[Optional[str], Optional[str]]], pin_dict: Dict[str, Port] - ) -> Dict[str, HasPassivePort]: + ) -> Dict[str, Union[Passive, HasPassivePort]]: """Generates pinning that can be passed into a footprint, given the pin assign dict from _remap_pin_assigns_list and pin dict from _generator_pin_dict. @@ -108,12 +108,12 @@ def _remap_to_footprint_pinning( Internal utility. """ - pinning: Dict[str, HasPassivePort] = {} + pinning: Dict[str, Union[Passive, HasPassivePort]] = {} for name, assign in pin_assigns.items(): assert name in pin_dict port = pin_dict[name] - if not isinstance(port, HasPassivePort): + if not isinstance(port, (Passive, HasPassivePort)): continue # ignore non-leaf ports assert assign[1] is not None, f"pin {name} missing pin number assignment" pinning[assign[1]] = port From eb79a320c72f21d77203b583f490916f975dda04 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 21:46:18 -0700 Subject: [PATCH 13/23] update netlists --- examples/BleJoystick/BleJoystick.net.ref | 8 ++++---- examples/BleJoystick/BleJoystick.svgpcb.js | 8 ++++---- examples/Datalogger/Datalogger.net.ref | 4 ++-- examples/Datalogger/Datalogger.svgpcb.js | 4 ++-- examples/EspLora/EspLora.net.ref | 4 ++-- examples/EspLora/EspLora.svgpcb.js | 4 ++-- examples/EspProgrammer/EspProgrammer.net.ref | 4 ++-- examples/EspProgrammer/EspProgrammer.svgpcb.js | 4 ++-- examples/Keyboard/Keyboard.net.ref | 4 ++-- examples/Keyboard/Keyboard.svgpcb.js | 4 ++-- examples/LedMatrix/LedMatrix.net.ref | 4 ++-- examples/LedMatrix/LedMatrix.svgpcb.js | 4 ++-- examples/Multimeter/Multimeter.net.ref | 8 ++++---- examples/Multimeter/Multimeter.svgpcb.js | 8 ++++---- examples/PcbBot/PcbBot.net.ref | 4 ++-- examples/PcbBot/PcbBot.svgpcb.js | 4 ++-- examples/PicoProbe/PicoProbe.net.ref | 8 ++++---- examples/PicoProbe/PicoProbe.svgpcb.js | 8 ++++---- examples/ProtectedCharger/ProtectedCharger.net.ref | 4 ++-- examples/ProtectedCharger/ProtectedCharger.svgpcb.js | 4 ++-- examples/SwdDebugger/SwdDebugger.net.ref | 4 ++-- examples/SwdDebugger/SwdDebugger.svgpcb.js | 4 ++-- examples/TestBlinkyArray/TestBlinkyArray.net.ref | 4 ++-- examples/TestBlinkyArray/TestBlinkyArray.svgpcb.js | 4 ++-- examples/TestBlinkyChain/TestBlinkyChain.net.ref | 4 ++-- examples/TestBlinkyChain/TestBlinkyChain.svgpcb.js | 4 ++-- examples/TestBlinkyComplete/TestBlinkyComplete.net.ref | 4 ++-- examples/TestBlinkyComplete/TestBlinkyComplete.svgpcb.js | 4 ++-- examples/TestBlinkyExpanded/TestBlinkyExpanded.net.ref | 4 ++-- examples/TestBlinkyExpanded/TestBlinkyExpanded.svgpcb.js | 4 ++-- examples/TestBlinkyImplicit/TestBlinkyImplicit.net.ref | 4 ++-- examples/TestBlinkyImplicit/TestBlinkyImplicit.svgpcb.js | 4 ++-- examples/TestBlinkyMicro/TestBlinkyMicro.net.ref | 4 ++-- examples/TestBlinkyMicro/TestBlinkyMicro.svgpcb.js | 4 ++-- examples/TestBlinkyPacked/TestBlinkyPacked.net.ref | 4 ++-- examples/TestBlinkyPacked/TestBlinkyPacked.svgpcb.js | 4 ++-- .../TestBlinkyWithLibrary/TestBlinkyWithLibrary.net.ref | 4 ++-- .../TestBlinkyWithLibrary/TestBlinkyWithLibrary.svgpcb.js | 4 ++-- .../TestBlinkyWithLibraryExport.net.ref | 4 ++-- .../TestBlinkyWithLibraryExport.svgpcb.js | 4 ++-- .../TestBlinkyWithModeledSchematicImport.net.ref | 4 ++-- .../TestBlinkyWithModeledSchematicImport.svgpcb.js | 4 ++-- .../TestBlinkyWithSchematicImport.net.ref | 4 ++-- .../TestBlinkyWithSchematicImport.svgpcb.js | 4 ++-- examples/TofArray/TofArray.net.ref | 4 ++-- examples/TofArray/TofArray.svgpcb.js | 4 ++-- examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net.ref | 4 ++-- examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js | 4 ++-- examples/UsbUart/UsbUart.net.ref | 4 ++-- examples/UsbUart/UsbUart.svgpcb.js | 4 ++-- 50 files changed, 112 insertions(+), 112 deletions(-) diff --git a/examples/BleJoystick/BleJoystick.net.ref b/examples/BleJoystick/BleJoystick.net.ref index 78f5ee14d..d130bf92e 100644 --- a/examples/BleJoystick/BleJoystick.net.ref +++ b/examples/BleJoystick/BleJoystick.net.ref @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "JR1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -77,7 +77,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "JR2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -389,7 +389,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dp.res")) + (property (name "edg_path") (value "mcu.usb_res.dp")) (property (name "edg_short_path") (value "mcu.usb_res.dp")) (property (name "edg_refdes") (value "JR7")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -401,7 +401,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dm.res")) + (property (name "edg_path") (value "mcu.usb_res.dm")) (property (name "edg_short_path") (value "mcu.usb_res.dm")) (property (name "edg_refdes") (value "JR8")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/BleJoystick/BleJoystick.svgpcb.js b/examples/BleJoystick/BleJoystick.svgpcb.js index 2c190607f..977631de9 100644 --- a/examples/BleJoystick/BleJoystick.svgpcb.js +++ b/examples/BleJoystick/BleJoystick.svgpcb.js @@ -25,12 +25,12 @@ const JJ2 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.235, 0.165), rotate: 0, id: 'JJ2' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const JR1 = board.add(R_0603_1608Metric, { translate: pt(1.083, 0.420), rotate: 0, id: 'JR1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const JR2 = board.add(R_0603_1608Metric, { translate: pt(1.239, 0.420), rotate: 0, id: 'JR2' @@ -160,12 +160,12 @@ const JC7 = board.add(C_0805_2012Metric, { translate: pt(0.840, 0.235), rotate: 0, id: 'JC7' }) -// mcu.usb_res.dp.res +// mcu.usb_res.dp const JR7 = board.add(R_0603_1608Metric, { translate: pt(0.658, 0.342), rotate: 0, id: 'JR7' }) -// mcu.usb_res.dm.res +// mcu.usb_res.dm const JR8 = board.add(R_0603_1608Metric, { translate: pt(0.814, 0.342), rotate: 0, id: 'JR8' diff --git a/examples/Datalogger/Datalogger.net.ref b/examples/Datalogger/Datalogger.net.ref index e9fa5da26..dfe7bb28d 100644 --- a/examples/Datalogger/Datalogger.net.ref +++ b/examples/Datalogger/Datalogger.net.ref @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_conn.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb_conn.cc_pull.cc1")) (property (name "edg_short_path") (value "usb_conn.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "")) @@ -41,7 +41,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_conn.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb_conn.cc_pull.cc2")) (property (name "edg_short_path") (value "usb_conn.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "")) diff --git a/examples/Datalogger/Datalogger.svgpcb.js b/examples/Datalogger/Datalogger.svgpcb.js index 7915795d4..92f543bb7 100644 --- a/examples/Datalogger/Datalogger.svgpcb.js +++ b/examples/Datalogger/Datalogger.svgpcb.js @@ -10,12 +10,12 @@ const J2 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.843, 1.867), rotate: 0, id: 'J2' }) -// usb_conn.cc_pull.cc1.res +// usb_conn.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(1.692, 2.122), rotate: 0, id: 'R1' }) -// usb_conn.cc_pull.cc2.res +// usb_conn.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.848, 2.122), rotate: 0, id: 'R2' diff --git a/examples/EspLora/EspLora.net.ref b/examples/EspLora/EspLora.net.ref index 12ad6870d..72e567a7c 100644 --- a/examples/EspLora/EspLora.net.ref +++ b/examples/EspLora/EspLora.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "LR1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "LR2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/EspLora/EspLora.svgpcb.js b/examples/EspLora/EspLora.svgpcb.js index 4eafcce46..4517ac630 100644 --- a/examples/EspLora/EspLora.svgpcb.js +++ b/examples/EspLora/EspLora.svgpcb.js @@ -20,12 +20,12 @@ const LJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.899, 1.905), rotate: 0, id: 'LJ1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const LR1 = board.add(R_0603_1608Metric, { translate: pt(2.748, 2.160), rotate: 0, id: 'LR1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const LR2 = board.add(R_0603_1608Metric, { translate: pt(2.904, 2.160), rotate: 0, id: 'LR2' diff --git a/examples/EspProgrammer/EspProgrammer.net.ref b/examples/EspProgrammer/EspProgrammer.net.ref index daee71497..a3ea97663 100644 --- a/examples/EspProgrammer/EspProgrammer.net.ref +++ b/examples/EspProgrammer/EspProgrammer.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_uart.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb_uart.cc_pull.cc1")) (property (name "edg_short_path") (value "usb_uart.cc_pull.cc1")) (property (name "edg_refdes") (value "UR1")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_uart.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb_uart.cc_pull.cc2")) (property (name "edg_short_path") (value "usb_uart.cc_pull.cc2")) (property (name "edg_refdes") (value "UR2")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/EspProgrammer/EspProgrammer.svgpcb.js b/examples/EspProgrammer/EspProgrammer.svgpcb.js index 3c8105bd8..c7ba0a390 100644 --- a/examples/EspProgrammer/EspProgrammer.svgpcb.js +++ b/examples/EspProgrammer/EspProgrammer.svgpcb.js @@ -20,12 +20,12 @@ const UJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.857, 0.165), rotate: 0, id: 'UJ1' }) -// usb_uart.cc_pull.cc1.res +// usb_uart.cc_pull.cc1 const UR1 = board.add(R_0402_1005Metric, { translate: pt(1.142, 0.019), rotate: 0, id: 'UR1' }) -// usb_uart.cc_pull.cc2.res +// usb_uart.cc_pull.cc2 const UR2 = board.add(R_0402_1005Metric, { translate: pt(1.142, 0.095), rotate: 0, id: 'UR2' diff --git a/examples/Keyboard/Keyboard.net.ref b/examples/Keyboard/Keyboard.net.ref index 6b674724e..30a51b3a1 100644 --- a/examples/Keyboard/Keyboard.net.ref +++ b/examples/Keyboard/Keyboard.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/Keyboard/Keyboard.svgpcb.js b/examples/Keyboard/Keyboard.svgpcb.js index 59c050780..437bec5dc 100644 --- a/examples/Keyboard/Keyboard.svgpcb.js +++ b/examples/Keyboard/Keyboard.svgpcb.js @@ -6,12 +6,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 2.783), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.058, 3.038), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.214, 3.038), rotate: 0, id: 'R2' diff --git a/examples/LedMatrix/LedMatrix.net.ref b/examples/LedMatrix/LedMatrix.net.ref index 642895c9f..2a20a90e2 100644 --- a/examples/LedMatrix/LedMatrix.net.ref +++ b/examples/LedMatrix/LedMatrix.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/LedMatrix/LedMatrix.svgpcb.js b/examples/LedMatrix/LedMatrix.svgpcb.js index fe463344e..c52774bec 100644 --- a/examples/LedMatrix/LedMatrix.svgpcb.js +++ b/examples/LedMatrix/LedMatrix.svgpcb.js @@ -21,12 +21,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 1.683), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.058, 1.938), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.214, 1.938), rotate: 0, id: 'R2' diff --git a/examples/Multimeter/Multimeter.net.ref b/examples/Multimeter/Multimeter.net.ref index 367eec4ed..3b983edc7 100644 --- a/examples/Multimeter/Multimeter.net.ref +++ b/examples/Multimeter/Multimeter.net.ref @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "data_usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "data_usb.cc_pull.cc1")) (property (name "edg_short_path") (value "data_usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -77,7 +77,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "data_usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "data_usb.cc_pull.cc2")) (property (name "edg_short_path") (value "data_usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -425,7 +425,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dp.res")) + (property (name "edg_path") (value "mcu.usb_res.dp")) (property (name "edg_short_path") (value "mcu.usb_res.dp")) (property (name "edg_refdes") (value "R6")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -437,7 +437,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dm.res")) + (property (name "edg_path") (value "mcu.usb_res.dm")) (property (name "edg_short_path") (value "mcu.usb_res.dm")) (property (name "edg_refdes") (value "R7")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/Multimeter/Multimeter.svgpcb.js b/examples/Multimeter/Multimeter.svgpcb.js index 0a94f219d..670a0e236 100644 --- a/examples/Multimeter/Multimeter.svgpcb.js +++ b/examples/Multimeter/Multimeter.svgpcb.js @@ -25,12 +25,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.365, 0.932), rotate: 0, id: 'J1' }) -// data_usb.cc_pull.cc1.res +// data_usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(2.213, 1.187), rotate: 0, id: 'R1' }) -// data_usb.cc_pull.cc2.res +// data_usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(2.369, 1.187), rotate: 0, id: 'R2' @@ -175,12 +175,12 @@ const C8 = board.add(C_0805_2012Metric, { translate: pt(0.732, 0.235), rotate: 0, id: 'C8' }) -// mcu.usb_res.dp.res +// mcu.usb_res.dp const R6 = board.add(R_0603_1608Metric, { translate: pt(0.550, 0.342), rotate: 0, id: 'R6' }) -// mcu.usb_res.dm.res +// mcu.usb_res.dm const R7 = board.add(R_0603_1608Metric, { translate: pt(0.706, 0.342), rotate: 0, id: 'R7' diff --git a/examples/PcbBot/PcbBot.net.ref b/examples/PcbBot/PcbBot.net.ref index 24f33e96b..4c0bd7ffd 100644 --- a/examples/PcbBot/PcbBot.net.ref +++ b/examples/PcbBot/PcbBot.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/PcbBot/PcbBot.svgpcb.js b/examples/PcbBot/PcbBot.svgpcb.js index bf1d48da7..c91681e02 100644 --- a/examples/PcbBot/PcbBot.svgpcb.js +++ b/examples/PcbBot/PcbBot.svgpcb.js @@ -20,12 +20,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(3.766, 1.905), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(3.615, 2.160), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(3.771, 2.160), rotate: 0, id: 'R2' diff --git a/examples/PicoProbe/PicoProbe.net.ref b/examples/PicoProbe/PicoProbe.net.ref index 537389881..4105c85bd 100644 --- a/examples/PicoProbe/PicoProbe.net.ref +++ b/examples/PicoProbe/PicoProbe.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "SR1")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "SR2")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) @@ -353,7 +353,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dp.res")) + (property (name "edg_path") (value "mcu.usb_res.dp")) (property (name "edg_short_path") (value "mcu.usb_res.dp")) (property (name "edg_refdes") (value "SR3")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -365,7 +365,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dm.res")) + (property (name "edg_path") (value "mcu.usb_res.dm")) (property (name "edg_short_path") (value "mcu.usb_res.dm")) (property (name "edg_refdes") (value "SR4")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/PicoProbe/PicoProbe.svgpcb.js b/examples/PicoProbe/PicoProbe.svgpcb.js index 824372000..3196118c0 100644 --- a/examples/PicoProbe/PicoProbe.svgpcb.js +++ b/examples/PicoProbe/PicoProbe.svgpcb.js @@ -20,12 +20,12 @@ const SJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 0.956), rotate: 0, id: 'SJ1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const SR1 = board.add(R_0402_1005Metric, { translate: pt(0.495, 0.810), rotate: 0, id: 'SR1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const SR2 = board.add(R_0402_1005Metric, { translate: pt(0.495, 0.886), rotate: 0, id: 'SR2' @@ -145,12 +145,12 @@ const SU5 = board.add(Resonator_SMD_Murata_CSTxExxV_3Pin_3_0x1_1mm, { translate: pt(0.394, 0.428), rotate: 0, id: 'SU5' }) -// mcu.usb_res.dp.res +// mcu.usb_res.dp const SR3 = board.add(R_0603_1608Metric, { translate: pt(0.562, 0.393), rotate: 0, id: 'SR3' }) -// mcu.usb_res.dm.res +// mcu.usb_res.dm const SR4 = board.add(R_0603_1608Metric, { translate: pt(0.718, 0.393), rotate: 0, id: 'SR4' diff --git a/examples/ProtectedCharger/ProtectedCharger.net.ref b/examples/ProtectedCharger/ProtectedCharger.net.ref index eb5fe603e..975cf2960 100644 --- a/examples/ProtectedCharger/ProtectedCharger.net.ref +++ b/examples/ProtectedCharger/ProtectedCharger.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/ProtectedCharger/ProtectedCharger.svgpcb.js b/examples/ProtectedCharger/ProtectedCharger.svgpcb.js index 9a9a70c6e..52d985bc8 100644 --- a/examples/ProtectedCharger/ProtectedCharger.svgpcb.js +++ b/examples/ProtectedCharger/ProtectedCharger.svgpcb.js @@ -20,12 +20,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.058, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.214, 0.420), rotate: 0, id: 'R2' diff --git a/examples/SwdDebugger/SwdDebugger.net.ref b/examples/SwdDebugger/SwdDebugger.net.ref index 76987738a..5b05af2c7 100644 --- a/examples/SwdDebugger/SwdDebugger.net.ref +++ b/examples/SwdDebugger/SwdDebugger.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "SR1")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0402_1005Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "SR2")) (property (name "edg_part") (value "0402WGF5101TCE (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/SwdDebugger/SwdDebugger.svgpcb.js b/examples/SwdDebugger/SwdDebugger.svgpcb.js index 9d4b044e4..b48cafd5d 100644 --- a/examples/SwdDebugger/SwdDebugger.svgpcb.js +++ b/examples/SwdDebugger/SwdDebugger.svgpcb.js @@ -20,12 +20,12 @@ const SJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.111, 0.165), rotate: 0, id: 'SJ1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const SR1 = board.add(R_0402_1005Metric, { translate: pt(1.396, 0.019), rotate: 0, id: 'SR1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const SR2 = board.add(R_0402_1005Metric, { translate: pt(1.396, 0.095), rotate: 0, id: 'SR2' diff --git a/examples/TestBlinkyArray/TestBlinkyArray.net.ref b/examples/TestBlinkyArray/TestBlinkyArray.net.ref index 688045de3..c79f00f58 100644 --- a/examples/TestBlinkyArray/TestBlinkyArray.net.ref +++ b/examples/TestBlinkyArray/TestBlinkyArray.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyArray/TestBlinkyArray.svgpcb.js b/examples/TestBlinkyArray/TestBlinkyArray.svgpcb.js index ed17db03d..0922a40c3 100644 --- a/examples/TestBlinkyArray/TestBlinkyArray.svgpcb.js +++ b/examples/TestBlinkyArray/TestBlinkyArray.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.750, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(2.598, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(2.754, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyChain/TestBlinkyChain.net.ref b/examples/TestBlinkyChain/TestBlinkyChain.net.ref index c3dde1847..21abf4314 100644 --- a/examples/TestBlinkyChain/TestBlinkyChain.net.ref +++ b/examples/TestBlinkyChain/TestBlinkyChain.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyChain/TestBlinkyChain.svgpcb.js b/examples/TestBlinkyChain/TestBlinkyChain.svgpcb.js index 924430fe3..0131c90ca 100644 --- a/examples/TestBlinkyChain/TestBlinkyChain.svgpcb.js +++ b/examples/TestBlinkyChain/TestBlinkyChain.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.111, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.960, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.116, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyComplete/TestBlinkyComplete.net.ref b/examples/TestBlinkyComplete/TestBlinkyComplete.net.ref index 5ef84d2b1..84f754732 100644 --- a/examples/TestBlinkyComplete/TestBlinkyComplete.net.ref +++ b/examples/TestBlinkyComplete/TestBlinkyComplete.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyComplete/TestBlinkyComplete.svgpcb.js b/examples/TestBlinkyComplete/TestBlinkyComplete.svgpcb.js index eddb56aeb..711c2ee7d 100644 --- a/examples/TestBlinkyComplete/TestBlinkyComplete.svgpcb.js +++ b/examples/TestBlinkyComplete/TestBlinkyComplete.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.111, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.960, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.116, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyExpanded/TestBlinkyExpanded.net.ref b/examples/TestBlinkyExpanded/TestBlinkyExpanded.net.ref index c3dde1847..21abf4314 100644 --- a/examples/TestBlinkyExpanded/TestBlinkyExpanded.net.ref +++ b/examples/TestBlinkyExpanded/TestBlinkyExpanded.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyExpanded/TestBlinkyExpanded.svgpcb.js b/examples/TestBlinkyExpanded/TestBlinkyExpanded.svgpcb.js index 924430fe3..0131c90ca 100644 --- a/examples/TestBlinkyExpanded/TestBlinkyExpanded.svgpcb.js +++ b/examples/TestBlinkyExpanded/TestBlinkyExpanded.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.111, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.960, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.116, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyImplicit/TestBlinkyImplicit.net.ref b/examples/TestBlinkyImplicit/TestBlinkyImplicit.net.ref index c3dde1847..21abf4314 100644 --- a/examples/TestBlinkyImplicit/TestBlinkyImplicit.net.ref +++ b/examples/TestBlinkyImplicit/TestBlinkyImplicit.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyImplicit/TestBlinkyImplicit.svgpcb.js b/examples/TestBlinkyImplicit/TestBlinkyImplicit.svgpcb.js index 924430fe3..0131c90ca 100644 --- a/examples/TestBlinkyImplicit/TestBlinkyImplicit.svgpcb.js +++ b/examples/TestBlinkyImplicit/TestBlinkyImplicit.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.111, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.960, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.116, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyMicro/TestBlinkyMicro.net.ref b/examples/TestBlinkyMicro/TestBlinkyMicro.net.ref index 836d2403d..e469e6002 100644 --- a/examples/TestBlinkyMicro/TestBlinkyMicro.net.ref +++ b/examples/TestBlinkyMicro/TestBlinkyMicro.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyMicro/TestBlinkyMicro.svgpcb.js b/examples/TestBlinkyMicro/TestBlinkyMicro.svgpcb.js index 3721e941d..fff8bc4c9 100644 --- a/examples/TestBlinkyMicro/TestBlinkyMicro.svgpcb.js +++ b/examples/TestBlinkyMicro/TestBlinkyMicro.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.750, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(2.598, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(2.754, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyPacked/TestBlinkyPacked.net.ref b/examples/TestBlinkyPacked/TestBlinkyPacked.net.ref index 62645f9b9..5ba1ac4ba 100644 --- a/examples/TestBlinkyPacked/TestBlinkyPacked.net.ref +++ b/examples/TestBlinkyPacked/TestBlinkyPacked.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyPacked/TestBlinkyPacked.svgpcb.js b/examples/TestBlinkyPacked/TestBlinkyPacked.svgpcb.js index d4c8f54c9..4ebe886a8 100644 --- a/examples/TestBlinkyPacked/TestBlinkyPacked.svgpcb.js +++ b/examples/TestBlinkyPacked/TestBlinkyPacked.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 1.907), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.058, 2.162), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.214, 2.162), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.net.ref b/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.net.ref index 42e1019ae..1e0360966 100644 --- a/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.net.ref +++ b/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.svgpcb.js b/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.svgpcb.js index 468ed7b04..facce1772 100644 --- a/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.svgpcb.js +++ b/examples/TestBlinkyWithLibrary/TestBlinkyWithLibrary.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.750, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(2.598, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(2.754, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.net.ref b/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.net.ref index 6e9d9329e..1ae691625 100644 --- a/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.net.ref +++ b/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.svgpcb.js b/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.svgpcb.js index 468ed7b04..facce1772 100644 --- a/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.svgpcb.js +++ b/examples/TestBlinkyWithLibraryExport/TestBlinkyWithLibraryExport.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(2.750, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(2.598, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(2.754, 0.420), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.net.ref b/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.net.ref index fa1238e85..2bdd9d690 100644 --- a/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.net.ref +++ b/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.svgpcb.js b/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.svgpcb.js index 463819dd8..edf7c2b0e 100644 --- a/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.svgpcb.js +++ b/examples/TestBlinkyWithModeledSchematicImport/TestBlinkyWithModeledSchematicImport.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.987, 1.907), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.835, 2.162), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.991, 2.162), rotate: 0, id: 'R2' diff --git a/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.net.ref b/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.net.ref index 893180881..1eb7db816 100644 --- a/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.net.ref +++ b/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.net.ref @@ -17,7 +17,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -29,7 +29,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.svgpcb.js b/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.svgpcb.js index 463819dd8..edf7c2b0e 100644 --- a/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.svgpcb.js +++ b/examples/TestBlinkyWithSchematicImport/TestBlinkyWithSchematicImport.svgpcb.js @@ -5,12 +5,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.987, 1.907), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(0.835, 2.162), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(0.991, 2.162), rotate: 0, id: 'R2' diff --git a/examples/TofArray/TofArray.net.ref b/examples/TofArray/TofArray.net.ref index 7fdc9e180..41faab2a8 100644 --- a/examples/TofArray/TofArray.net.ref +++ b/examples/TofArray/TofArray.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/TofArray/TofArray.svgpcb.js b/examples/TofArray/TofArray.svgpcb.js index a8355bd35..7fb384a61 100644 --- a/examples/TofArray/TofArray.svgpcb.js +++ b/examples/TofArray/TofArray.svgpcb.js @@ -20,12 +20,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.992, 0.165), rotate: 0, id: 'J1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(1.841, 0.420), rotate: 0, id: 'R1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.997, 0.420), rotate: 0, id: 'R2' diff --git a/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net.ref b/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net.ref index 9d420c790..2468614a1 100644 --- a/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net.ref +++ b/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb.cc_pull.cc1")) (property (name "edg_short_path") (value "usb.cc_pull.cc1")) (property (name "edg_refdes") (value "FR1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb.cc_pull.cc2")) (property (name "edg_short_path") (value "usb.cc_pull.cc2")) (property (name "edg_refdes") (value "FR2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js b/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js index 4faa2eb49..aa30bafae 100644 --- a/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js +++ b/examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js @@ -20,12 +20,12 @@ const FJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.224, 0.165), rotate: 0, id: 'FJ1' }) -// usb.cc_pull.cc1.res +// usb.cc_pull.cc1 const FR1 = board.add(R_0603_1608Metric, { translate: pt(1.072, 0.420), rotate: 0, id: 'FR1' }) -// usb.cc_pull.cc2.res +// usb.cc_pull.cc2 const FR2 = board.add(R_0603_1608Metric, { translate: pt(1.228, 0.420), rotate: 0, id: 'FR2' diff --git a/examples/UsbUart/UsbUart.net.ref b/examples/UsbUart/UsbUart.net.ref index 6f0928adb..a847c7fe1 100644 --- a/examples/UsbUart/UsbUart.net.ref +++ b/examples/UsbUart/UsbUart.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_uart.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb_uart.cc_pull.cc1")) (property (name "edg_short_path") (value "usb_uart.cc_pull.cc1")) (property (name "edg_refdes") (value "UR1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_uart.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb_uart.cc_pull.cc2")) (property (name "edg_short_path") (value "usb_uart.cc_pull.cc2")) (property (name "edg_refdes") (value "UR2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/UsbUart/UsbUart.svgpcb.js b/examples/UsbUart/UsbUart.svgpcb.js index 7ce7a8e11..55568efca 100644 --- a/examples/UsbUart/UsbUart.svgpcb.js +++ b/examples/UsbUart/UsbUart.svgpcb.js @@ -20,12 +20,12 @@ const UJ1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(0.209, 0.165), rotate: 0, id: 'UJ1' }) -// usb_uart.cc_pull.cc1.res +// usb_uart.cc_pull.cc1 const UR1 = board.add(R_0603_1608Metric, { translate: pt(0.058, 0.420), rotate: 0, id: 'UR1' }) -// usb_uart.cc_pull.cc2.res +// usb_uart.cc_pull.cc2 const UR2 = board.add(R_0603_1608Metric, { translate: pt(0.214, 0.420), rotate: 0, id: 'UR2' From d5c9ec3554d33278f21b9bb8c64c921586e30a9e Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 21:54:34 -0700 Subject: [PATCH 14/23] update netlists --- edg/circuits/UsbBitBang.py | 8 ++++---- examples/Fcml/Fcml.net.ref | 18 +++++++++--------- examples/Fcml/Fcml.svgpcb.js | 18 +++++++++--------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/edg/circuits/UsbBitBang.py b/edg/circuits/UsbBitBang.py index ce1591a28..bac624bd4 100644 --- a/edg/circuits/UsbBitBang.py +++ b/edg/circuits/UsbBitBang.py @@ -51,11 +51,11 @@ def contents(self) -> None: self.dp_pull_res = self.Block(Resistor(1.5 * kOhm(tol=0.05))) self.connect(self.dp_pull_res.a, self.dp_pull.net) self.dp_res = self.Block(Resistor(68 * Ohm(tol=0.05))) - self.connect(self.dp_res.a, self.dp.net) - self.connect(self.dp_pull_res.b, self.dp_res.b, self.usb.dp) + self.connect(self.dp_res.b, self.dp.net) + self.connect(self.dp_pull_res.b, self.dp_res.a, self.usb.dp) self.dm_res = self.Block(Resistor(68 * Ohm(tol=0.05))) - self.connect(self.dm_res.a, self.dm.net) - self.connect(self.dm_res.b, self.usb.dm) + self.connect(self.dm_res.b, self.dm.net) + self.connect(self.dm_res.a, self.usb.dm) def connected_from(self, dp_pull: Port[DigitalLink], dp: Port[DigitalLink], dm: Port[DigitalLink]) -> "UsbBitBang": builder.block().connect(dp_pull, self.dp_pull) diff --git a/examples/Fcml/Fcml.net.ref b/examples/Fcml/Fcml.net.ref index 171e420b8..a50690c83 100644 --- a/examples/Fcml/Fcml.net.ref +++ b/examples/Fcml/Fcml.net.ref @@ -53,7 +53,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_mcu.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb_mcu.cc_pull.cc1")) (property (name "edg_short_path") (value "usb_mcu.cc_pull.cc1")) (property (name "edg_refdes") (value "R1")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -65,7 +65,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_mcu.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb_mcu.cc_pull.cc2")) (property (name "edg_short_path") (value "usb_mcu.cc_pull.cc2")) (property (name "edg_refdes") (value "R2")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -89,7 +89,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_fpga.cc_pull.cc1.res")) + (property (name "edg_path") (value "usb_fpga.cc_pull.cc1")) (property (name "edg_short_path") (value "usb_fpga.cc_pull.cc1")) (property (name "edg_refdes") (value "R3")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -101,7 +101,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "cc_pull")) (property (name "Sheetfile") (value "edg.parts.connector.UsbPorts.UsbCcPulldownResistor")) - (property (name "edg_path") (value "usb_fpga.cc_pull.cc2.res")) + (property (name "edg_path") (value "usb_fpga.cc_pull.cc2")) (property (name "edg_short_path") (value "usb_fpga.cc_pull.cc2")) (property (name "edg_refdes") (value "R4")) (property (name "edg_part") (value "0603WAF5101T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -1385,7 +1385,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_fpga_bitbang")) (property (name "Sheetfile") (value "edg.circuits.UsbBitBang.UsbBitBang")) - (property (name "edg_path") (value "usb_fpga_bitbang.dp_pull_res.res")) + (property (name "edg_path") (value "usb_fpga_bitbang.dp_pull_res")) (property (name "edg_short_path") (value "usb_fpga_bitbang.dp_pull_res")) (property (name "edg_refdes") (value "R21")) (property (name "edg_part") (value "0603WAF1501T5E (UNI-ROYAL(Uniroyal Elec))")) @@ -1397,7 +1397,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_fpga_bitbang")) (property (name "Sheetfile") (value "edg.circuits.UsbBitBang.UsbBitBang")) - (property (name "edg_path") (value "usb_fpga_bitbang.dp_res.res")) + (property (name "edg_path") (value "usb_fpga_bitbang.dp_res")) (property (name "edg_short_path") (value "usb_fpga_bitbang.dp_res")) (property (name "edg_refdes") (value "R22")) (property (name "edg_part") (value "0603WAF680JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -1409,7 +1409,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_fpga_bitbang")) (property (name "Sheetfile") (value "edg.circuits.UsbBitBang.UsbBitBang")) - (property (name "edg_path") (value "usb_fpga_bitbang.dm_res.res")) + (property (name "edg_path") (value "usb_fpga_bitbang.dm_res")) (property (name "edg_short_path") (value "usb_fpga_bitbang.dm_res")) (property (name "edg_refdes") (value "R23")) (property (name "edg_part") (value "0603WAF680JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -1649,7 +1649,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dp.res")) + (property (name "edg_path") (value "mcu.usb_res.dp")) (property (name "edg_short_path") (value "mcu.usb_res.dp")) (property (name "edg_refdes") (value "R24")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) @@ -1661,7 +1661,7 @@ (footprint "Resistor_SMD:R_0603_1608Metric") (property (name "Sheetname") (value "usb_res")) (property (name "Sheetfile") (value "edg.circuits.UsbSeriesResistor.UsbSeriesResistor")) - (property (name "edg_path") (value "mcu.usb_res.dm.res")) + (property (name "edg_path") (value "mcu.usb_res.dm")) (property (name "edg_short_path") (value "mcu.usb_res.dm")) (property (name "edg_refdes") (value "R25")) (property (name "edg_part") (value "0603WAF270JT5E (UNI-ROYAL(Uniroyal Elec))")) diff --git a/examples/Fcml/Fcml.svgpcb.js b/examples/Fcml/Fcml.svgpcb.js index 46135a11e..0aa93df95 100644 --- a/examples/Fcml/Fcml.svgpcb.js +++ b/examples/Fcml/Fcml.svgpcb.js @@ -20,12 +20,12 @@ const J1 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.237, 1.501), rotate: 0, id: 'J1' }) -// usb_mcu.cc_pull.cc1.res +// usb_mcu.cc_pull.cc1 const R1 = board.add(R_0603_1608Metric, { translate: pt(1.086, 1.756), rotate: 0, id: 'R1' }) -// usb_mcu.cc_pull.cc2.res +// usb_mcu.cc_pull.cc2 const R2 = board.add(R_0603_1608Metric, { translate: pt(1.242, 1.756), rotate: 0, id: 'R2' @@ -35,12 +35,12 @@ const J2 = board.add(USB_C_Receptacle_XKB_U262_16XN_4BVC11, { translate: pt(1.774, 1.501), rotate: 0, id: 'J2' }) -// usb_fpga.cc_pull.cc1.res +// usb_fpga.cc_pull.cc1 const R3 = board.add(R_0603_1608Metric, { translate: pt(1.623, 1.756), rotate: 0, id: 'R3' }) -// usb_fpga.cc_pull.cc2.res +// usb_fpga.cc_pull.cc2 const R4 = board.add(R_0603_1608Metric, { translate: pt(1.779, 1.756), rotate: 0, id: 'R4' @@ -575,17 +575,17 @@ const R20 = board.add(R_0603_1608Metric, { translate: pt(3.371, 1.656), rotate: 0, id: 'R20' }) -// usb_fpga_bitbang.dp_pull_res.res +// usb_fpga_bitbang.dp_pull_res const R21 = board.add(R_0603_1608Metric, { translate: pt(1.418, 2.264), rotate: 0, id: 'R21' }) -// usb_fpga_bitbang.dp_res.res +// usb_fpga_bitbang.dp_res const R22 = board.add(R_0603_1608Metric, { translate: pt(1.418, 2.361), rotate: 0, id: 'R22' }) -// usb_fpga_bitbang.dm_res.res +// usb_fpga_bitbang.dm_res const R23 = board.add(R_0603_1608Metric, { translate: pt(1.418, 2.458), rotate: 0, id: 'R23' @@ -685,12 +685,12 @@ const C60 = board.add(C_0603_1608Metric, { translate: pt(2.802, 0.755), rotate: 0, id: 'C60' }) -// mcu.usb_res.dp.res +// mcu.usb_res.dp const R24 = board.add(R_0603_1608Metric, { translate: pt(2.023, 0.852), rotate: 0, id: 'R24' }) -// mcu.usb_res.dm.res +// mcu.usb_res.dm const R25 = board.add(R_0603_1608Metric, { translate: pt(2.179, 0.852), rotate: 0, id: 'R25' From 421ad02dc50f0041907dbb813a8467e7b56d6891 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 23:07:25 -0700 Subject: [PATCH 15/23] Rename current_drawn -> current_draw --- edg/abstract_parts/AnalogSwitch.py | 4 +- edg/abstract_parts/FerriteBead.py | 4 +- edg/abstract_parts/Fuse.py | 4 +- edg/abstract_parts/IdealIoController.py | 8 ++-- edg/abstract_parts/Inductor.py | 2 +- edg/abstract_parts/IoController.py | 8 ++-- edg/abstract_parts/Jumper.py | 6 +-- edg/abstract_parts/LinearRegulator.py | 4 +- edg/abstract_parts/Resistor.py | 14 +++---- edg/abstract_parts/SolidStateRelay.py | 2 +- edg/abstract_parts/Switch.py | 6 +-- .../SwitchingVoltageRegulator.py | 4 +- edg/abstract_parts/VoltageRegulator.py | 2 +- edg/abstract_parts/ZenerDiode.py | 2 +- edg/abstract_parts/test_ideal_circuit.py | 2 +- edg/circuits/BootstrapVoltageAdder.py | 2 +- edg/circuits/DigitalAmplifiers.py | 10 ++--- edg/circuits/LevelShifter.py | 2 +- edg/circuits/OpampCurrentSensor.py | 2 +- edg/circuits/PassiveFilters.py | 10 ++--- edg/circuits/PowerCircuits.py | 10 ++--- edg/circuits/PowerConditioning.py | 22 +++++----- edg/circuits/ResistiveDivider.py | 6 +-- edg/circuits/ResistiveSensor.py | 2 +- edg/circuits/SwitchMatrix.py | 4 +- edg/circuits/UsbBitBang.py | 2 +- edg/circuits/VoltageClamping.py | 2 +- edg/electronics_interfaces/AnalogPort.py | 21 ++++++---- .../CircuitPackingBlock.py | 2 +- edg/electronics_interfaces/DigitalPorts.py | 23 ++++++---- edg/electronics_interfaces/DummyDevices.py | 6 +-- edg/electronics_interfaces/MergedBlocks.py | 6 +-- edg/electronics_interfaces/VoltageDummy.py | 7 +++- edg/electronics_interfaces/VoltagePorts.py | 42 ++++++++++++------- edg/parts/microcontroller/Rp2040.py | 4 +- edg/parts/power/Batteries.py | 2 +- edg/parts/power/BatteryProtector_S8261A.py | 4 +- .../power/converter/AnalogDevices_Boost.py | 2 +- edg/parts/power/converter/Ap3418.py | 4 +- edg/parts/power/converter/CustomBuck.py | 4 +- edg/parts/power/converter/CustomBuckBoost.py | 2 +- edg/parts/power/converter/DiodesInc_Boost.py | 4 +- edg/parts/power/converter/Mp2722.py | 6 +-- .../power/converter/TexasInstruments_Boost.py | 8 ++-- .../power/converter/TexasInstruments_Buck.py | 14 +++---- .../converter/TexasInstruments_SwitchedCap.py | 4 +- edg/parts/power/converter/Torex_Boost.py | 2 +- edg/parts/power/gate_driver/Ir2301.py | 4 +- edg/parts/power/gate_driver/Ncp3420.py | 2 +- edg/parts/power/gate_driver/Ucc27282.py | 2 +- edg/parts/power/motor/Bldc_Drv8313.py | 4 +- edg/parts/power/motor/MotorDriver_Drv8833.py | 8 ++-- edg/parts/power/motor/MotorDriver_Drv8870.py | 2 +- edg/parts/power/motor/MotorDriver_L293dd.py | 8 ++-- edg/parts/power/motor/StepperDriver_A4988.py | 4 +- examples/test_datalogger.py | 2 +- examples/test_fcml.py | 14 +++---- examples/test_iot_display.py | 4 +- examples/test_lora.py | 2 +- examples/test_usb_source_measure.py | 4 +- 60 files changed, 200 insertions(+), 173 deletions(-) diff --git a/edg/abstract_parts/AnalogSwitch.py b/edg/abstract_parts/AnalogSwitch.py index 5ae73027d..975695fbd 100644 --- a/edg/abstract_parts/AnalogSwitch.py +++ b/edg/abstract_parts/AnalogSwitch.py @@ -150,7 +150,7 @@ def generate(self) -> None: input = self.inputs.append_elt( AnalogSink( voltage_limits=self.device.analog_voltage_limits, # this device only, voltages propagated - current_draw=self.out.link().current_drawn, + current_draw=self.out.link().current_draw, impedance=self.out.link().sink_impedance + self.device.analog_on_resistance, ), elt, @@ -184,7 +184,7 @@ def __init__(self) -> None: self.input = self.Port( AnalogSink( voltage_limits=self.device.analog_voltage_limits, # this device only, voltages propagated - current_draw=self.outputs.hull(lambda x: x.link().current_drawn), + current_draw=self.outputs.hull(lambda x: x.link().current_draw), impedance=self.device.analog_on_resistance + self.outputs.hull(lambda x: x.link().sink_impedance), ) ) diff --git a/edg/abstract_parts/FerriteBead.py b/edg/abstract_parts/FerriteBead.py index b3a3ad5bd..e9f4a8c86 100644 --- a/edg/abstract_parts/FerriteBead.py +++ b/edg/abstract_parts/FerriteBead.py @@ -127,14 +127,14 @@ def __init__(self, hf_impedance: RangeLike = RangeExpr.ALL, dc_resistance: Range self.fb = self.Block( FerriteBead( - current=self.pwr_out.link().current_drawn, hf_impedance=hf_impedance, dc_resistance=dc_resistance + current=self.pwr_out.link().current_draw, hf_impedance=hf_impedance, dc_resistance=dc_resistance ) ) self.connect(self.pwr_in.net, self.fb.a) self.connect(self.pwr_out.net, self.fb.b) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) self.assign(self.pwr_out.current_limits, self.fb.actual_current_rating) def connected( diff --git a/edg/abstract_parts/Fuse.py b/edg/abstract_parts/Fuse.py index f33e04e7f..5c33e3c0d 100644 --- a/edg/abstract_parts/Fuse.py +++ b/edg/abstract_parts/Fuse.py @@ -96,7 +96,7 @@ def __init__(self, trip_current: RangeLike) -> None: self.fuse = self.Block( self.FUSE_TYPE( trip_current=trip_current, - hold_current=(self.pwr_out.link().current_drawn.upper(), float("inf")), + hold_current=(self.pwr_out.link().current_draw.upper(), float("inf")), voltage=self.pwr_in.link().voltage, ) ) @@ -104,7 +104,7 @@ def __init__(self, trip_current: RangeLike) -> None: self.connect(self.pwr_out.net, self.fuse.b) self.assign(self.pwr_in.voltage_limits, self.fuse.actual_voltage_rating) # TODO: eventually needs a ground ref - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) self.assign(self.pwr_out.current_limits, (0, self.fuse.actual_hold_current.lower())) def connected( diff --git a/edg/abstract_parts/IdealIoController.py b/edg/abstract_parts/IdealIoController.py index 7ae248813..9ee1479a4 100644 --- a/edg/abstract_parts/IdealIoController.py +++ b/edg/abstract_parts/IdealIoController.py @@ -62,8 +62,8 @@ def generate(self) -> None: for elt in self.get(self.dac.requested()): aout = self.dac.append_elt(AnalogSource.from_supply(self.gnd, self.pwr), elt) io_current_draw_builder = io_current_draw_builder + ( - aout.link().current_drawn.lower().min(0), - aout.link().current_drawn.upper().max(0), + aout.link().current_draw.lower().min(0), + aout.link().current_draw.upper().max(0), ) dio_model = DigitalBidir.from_supply(self.gnd, self.pwr, pullup_capable=True, pulldown_capable=True) @@ -72,8 +72,8 @@ def generate(self) -> None: for elt in self.get(self.gpio.requested()): dio = self.gpio.append_elt(dio_model, elt) io_current_draw_builder = io_current_draw_builder + ( - dio.link().current_drawn.lower().min(0), - dio.link().current_drawn.upper().max(0), + dio.link().current_draw.lower().min(0), + dio.link().current_draw.upper().max(0), ) self.spi.defined() diff --git a/edg/abstract_parts/Inductor.py b/edg/abstract_parts/Inductor.py index e85f82874..be95a99a8 100644 --- a/edg/abstract_parts/Inductor.py +++ b/edg/abstract_parts/Inductor.py @@ -202,7 +202,7 @@ def __init__( self.connect(self.pwr_in.net, self.ind.a) self.connect(self.pwr_out.net, self.ind.b) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) def connected( self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optional[Port[VoltageLink]] = None diff --git a/edg/abstract_parts/IoController.py b/edg/abstract_parts/IoController.py index 291ffd4a9..4826c02da 100644 --- a/edg/abstract_parts/IoController.py +++ b/edg/abstract_parts/IoController.py @@ -236,8 +236,8 @@ def _instantiate_from( if isinstance(io_port, DigitalBidir): io_current_draw_builder = io_current_draw_builder + ( - io_port.link().current_drawn.lower().min(0), - io_port.link().current_drawn.upper().max(0), + io_port.link().current_draw.lower().min(0), + io_port.link().current_draw.upper().max(0), ) elif isinstance(io_port, AnalogSink): pass # assumed no current draw into a sink @@ -245,8 +245,8 @@ def _instantiate_from( pass # assumed no current draw elif isinstance(io_port, AnalogSource): io_current_draw_builder = io_current_draw_builder + ( - io_port.link().current_drawn.lower().min(0), - io_port.link().current_drawn.upper().max(0), + io_port.link().current_draw.lower().min(0), + io_port.link().current_draw.upper().max(0), ) # TODO: recurse into bundles, really needs a more unified way of handling current draw diff --git a/edg/abstract_parts/Jumper.py b/edg/abstract_parts/Jumper.py index 4eed75f2b..43c2fdbe4 100644 --- a/edg/abstract_parts/Jumper.py +++ b/edg/abstract_parts/Jumper.py @@ -36,7 +36,7 @@ def __init__(self) -> None: self.input = self.Port(VoltageSink(current_draw=RangeExpr(), reverse_voltage_out=RangeExpr()), [Input]) self.output = self.Port( VoltageSource( - voltage_out=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_drawn + voltage_out=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_draw ), [Output], ) @@ -45,7 +45,7 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() self.device = self.Block(Jumper()) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.assign(self.input.reverse_voltage_out, self.output.link().reverse_voltage) self.connect(self.input.net, self.device.a) self.connect(self.output.net, self.device.b) @@ -64,6 +64,6 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() self.device = self.Block(Jumper()) - self.assign(self.input.current_draw, self.output.link().current_drawn) # for model purposes, treat as connected + self.assign(self.input.current_draw, self.output.link().current_draw) # for model purposes, treat as connected self.connect(self.input.net, self.device.a) self.connect(self.output.net, self.device.b) diff --git a/edg/abstract_parts/LinearRegulator.py b/edg/abstract_parts/LinearRegulator.py index 94581515d..b31779ae0 100644 --- a/edg/abstract_parts/LinearRegulator.py +++ b/edg/abstract_parts/LinearRegulator.py @@ -28,7 +28,7 @@ def contents(self) -> None: super().contents() effective_output_voltage = self.output_voltage.intersect((0, self.pwr_in.link().voltage.upper())) self.gnd.init_from(Ground()) - self.pwr_in.init_from(VoltageSink(current_draw=self.pwr_out.link().current_drawn)) + self.pwr_in.init_from(VoltageSink(current_draw=self.pwr_out.link().current_draw)) self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) self.reset.init_from(DigitalSink()) @@ -55,7 +55,7 @@ def __init__(self) -> None: VoltageSource(voltage_out=self.RangeExpr(), current_limits=RangeExpr()), # parameters set by subtype [Output], ) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn + self.actual_quiescent_current) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw + self.actual_quiescent_current) self.require( self.pwr_out.voltage_out.lower() + self.actual_dropout.upper() <= self.pwr_in.link().voltage.lower(), diff --git a/edg/abstract_parts/Resistor.py b/edg/abstract_parts/Resistor.py index 1d3d6865c..b50f50cc3 100644 --- a/edg/abstract_parts/Resistor.py +++ b/edg/abstract_parts/Resistor.py @@ -304,11 +304,11 @@ def __init__(self, resistance: RangeLike) -> None: VoltageSource(voltage_out=self.pwr_in.link().voltage), # ignore voltage drop [Output], ) - current_draw = self.pwr_out.link().current_drawn.abs() + current_draw = self.pwr_out.link().current_draw.abs() self.res = self.Block(Resistor(resistance=self.resistance, power=current_draw * current_draw * self.resistance)) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) self.connect(self.pwr_in.net, self.res.a) self.connect(self.pwr_out.net, self.res.b) @@ -434,7 +434,7 @@ def __init__(self, resistance: RangeLike) -> None: self.assign(self.input.impedance, self.output.link().sink_impedance + self.res.actual_resistance) self.assign( - self.res.power, self.input.link().current_drawn * self.input.link().current_drawn * self.res.resistance + self.res.power, self.input.link().current_draw * self.input.link().current_draw * self.res.resistance ) self.connect(self.input.net, self.res.a) self.connect(self.output.net, self.res.b) @@ -470,12 +470,12 @@ def __init__(self, resistance: RangeLike) -> None: ), [Output], ) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.res = self.Block( Resistor( resistance=resistance, - power=self.input.link().current_drawn * self.input.link().current_drawn * resistance, + power=self.input.link().current_draw * self.input.link().current_draw * resistance, ) ) self.actual_resistance = self.Parameter(RangeExpr(self.res.actual_resistance)) @@ -536,7 +536,7 @@ def __init__(self, resistance: RangeLike) -> None: self.res = self.Block( Resistor( resistance=resistance, - power=self.interior.link().current_drawn * self.interior.link().current_drawn * resistance, + power=self.interior.link().current_draw * self.interior.link().current_draw * resistance, ) ) self.actual_resistance = self.Parameter(RangeExpr(self.res.actual_resistance)) @@ -545,7 +545,7 @@ def __init__(self, resistance: RangeLike) -> None: self.connect(self.interior.net, self.res.b) self.assign(self.exterior.voltage_out, self.interior.link().voltage) - self.assign(self.exterior.current_draw, self.interior.link().current_drawn) + self.assign(self.exterior.current_draw, self.interior.link().current_draw) self.assign(self.exterior.voltage_limits, self.interior.link().voltage_limits) self.assign( self.exterior.current_limits, self.interior.link().current_limits diff --git a/edg/abstract_parts/SolidStateRelay.py b/edg/abstract_parts/SolidStateRelay.py index 98f05dc6f..94265963e 100644 --- a/edg/abstract_parts/SolidStateRelay.py +++ b/edg/abstract_parts/SolidStateRelay.py @@ -69,7 +69,7 @@ def __init__(self) -> None: self.connect(self.pwr_out.net, self.ic.fetb) self.assign(self.pwr_in.voltage_limits, self.ic.load_voltage_limit) # TODO: assumed magic ground - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) self.assign(self.pwr_out.current_limits, self.ic.load_current_limit) self.assign(self.signal.current_draw, self.signal.link().voltage / self.res.actual_resistance) diff --git a/edg/abstract_parts/Switch.py b/edg/abstract_parts/Switch.py index afbf3c44b..5f4a6e538 100644 --- a/edg/abstract_parts/Switch.py +++ b/edg/abstract_parts/Switch.py @@ -98,7 +98,7 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - self.package = self.Block(Switch(current=self.out.link().current_drawn, voltage=self.out.link().voltage)) + self.package = self.Block(Switch(current=self.out.link().current_draw, voltage=self.out.link().voltage)) self.connect(self.out.net, self.package.sw) self.connect(self.gnd.net, self.package.com) @@ -130,7 +130,7 @@ def contents(self) -> None: self.package = self.Block( RotaryEncoder( - current=self.a.link().current_drawn.hull(self.b.link().current_drawn), + current=self.a.link().current_draw.hull(self.b.link().current_draw), voltage=self.a.link().voltage.hull(self.b.link().voltage), ) ) @@ -194,7 +194,7 @@ def contents(self) -> None: self.package = self.Block( DirectionSwitch( - current=self.a.link().current_drawn.hull(self.b.link().current_drawn), + current=self.a.link().current_draw.hull(self.b.link().current_draw), voltage=self.a.link().voltage.hull(self.b.link().voltage), ) ) diff --git a/edg/abstract_parts/SwitchingVoltageRegulator.py b/edg/abstract_parts/SwitchingVoltageRegulator.py index 31d52ed77..29a2b3686 100644 --- a/edg/abstract_parts/SwitchingVoltageRegulator.py +++ b/edg/abstract_parts/SwitchingVoltageRegulator.py @@ -76,7 +76,7 @@ def contents(self) -> None: self.gnd.init_from(Ground()) self.pwr_in.init_from( VoltageSink( - current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_drawn + current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) @@ -108,7 +108,7 @@ def contents(self) -> None: self.gnd.init_from(Ground()) self.pwr_in.init_from( VoltageSink( - current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_drawn + current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) diff --git a/edg/abstract_parts/VoltageRegulator.py b/edg/abstract_parts/VoltageRegulator.py index aab739e5f..c7299335a 100644 --- a/edg/abstract_parts/VoltageRegulator.py +++ b/edg/abstract_parts/VoltageRegulator.py @@ -79,7 +79,7 @@ def contents(self) -> None: self.gnd.init_from(Ground()) self.pwr_in.init_from( VoltageSink( - current_draw=self.output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_drawn + current_draw=self.output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) self.pwr_out.init_from(VoltageSource(voltage_out=self.output_voltage)) diff --git a/edg/abstract_parts/ZenerDiode.py b/edg/abstract_parts/ZenerDiode.py index 581397304..fda9ce145 100644 --- a/edg/abstract_parts/ZenerDiode.py +++ b/edg/abstract_parts/ZenerDiode.py @@ -107,7 +107,7 @@ def __init__(self, voltage: RangeLike): ), [Output], ) - self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn) + self.assign(self.signal_in.current_draw, self.signal_out.link().current_draw) self.connect(self.signal_in.net, self.signal_out.net, self.diode.cathode) self.connect(self.gnd.net, self.diode.anode) diff --git a/edg/abstract_parts/test_ideal_circuit.py b/edg/abstract_parts/test_ideal_circuit.py index ee770e136..445838a9a 100644 --- a/edg/abstract_parts/test_ideal_circuit.py +++ b/edg/abstract_parts/test_ideal_circuit.py @@ -25,7 +25,7 @@ def __init__(self) -> None: self.connect(self.mcu.pwr, self.reg.pwr_out) self.mcu_io = self.Block(DummyDigitalSink()).connected(self.mcu.gpio.request("test")) - self.require(self.pwr.current_drawn == 3 * Amp(tol=0)) + self.require(self.pwr.current_draw == 3 * Amp(tol=0)) self.require(self.reg_draw.voltage == 2 * Volt(tol=0)) diff --git a/edg/circuits/BootstrapVoltageAdder.py b/edg/circuits/BootstrapVoltageAdder.py index 5cef84e28..edae1643b 100644 --- a/edg/circuits/BootstrapVoltageAdder.py +++ b/edg/circuits/BootstrapVoltageAdder.py @@ -26,7 +26,7 @@ def contents(self) -> None: super().contents() # TODO model diode forward voltage drops - out_current = self.out_pos.link().current_drawn.hull(self.out_neg.link().current_drawn) + out_current = self.out_pos.link().current_draw.hull(self.out_neg.link().current_draw) diode_model = Diode( reverse_voltage=self.pwm.link().voltage.hull(0 * Volt(tol=0)), current=out_current, diff --git a/edg/circuits/DigitalAmplifiers.py b/edg/circuits/DigitalAmplifiers.py index d0988ac1e..8db96edae 100644 --- a/edg/circuits/DigitalAmplifiers.py +++ b/edg/circuits/DigitalAmplifiers.py @@ -35,7 +35,7 @@ def contents(self) -> None: self.fet = self.Block( SwitchFet.PFet( drain_voltage=self.pwr_in.link().voltage - self.gnd.link().voltage, - drain_current=self.pwr_out.link().current_drawn, + drain_current=self.pwr_out.link().current_draw, gate_voltage=self.control.link().voltage - self.gnd.link().voltage, gate_threshold_voltage=( self.control.link().output_thresholds.lower() - self.gnd.link().voltage.lower(), @@ -47,7 +47,7 @@ def contents(self) -> None: ) ) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) self.connect(self.pwr_in.net, self.fet.source) self.connect(self.control.net, self.fet.gate) @@ -121,7 +121,7 @@ def generate(self) -> None: self.drv = self.Block( SwitchFet.PFet( drain_voltage=pwr_voltage, - drain_current=self.output.link().current_drawn, + drain_current=self.output.link().current_draw, gate_voltage=pass_gate_voltage, rds_on=(0, self.max_rds), frequency=self.frequency, @@ -133,7 +133,7 @@ def generate(self) -> None: ) conversions: Dict[str, HasPassivePort] = { - "pwr": VoltageSink(current_draw=self.output.link().current_drawn), + "pwr": VoltageSink(current_draw=self.output.link().current_draw), "output": VoltageSource( voltage_out=self.pwr.link().voltage, current_limits=self.drv.actual_drain_current_rating, @@ -183,7 +183,7 @@ def contents(self) -> None: self.drv = self.Block( SwitchFet.NFet( drain_voltage=self.output.link().voltage, - drain_current=self.output.link().current_drawn, + drain_current=self.output.link().current_draw, gate_voltage=self.control.link().voltage, rds_on=(0, self.max_rds), frequency=self.frequency, diff --git a/edg/circuits/LevelShifter.py b/edg/circuits/LevelShifter.py index c583a3374..3889d57f2 100644 --- a/edg/circuits/LevelShifter.py +++ b/edg/circuits/LevelShifter.py @@ -43,7 +43,7 @@ def generate(self) -> None: self.fet = self.Block( Fet.NFet( drain_voltage=self.hv_pwr.link().voltage.hull(self.hv_io.link().voltage), - drain_current=self.lv_io.link().current_drawn.hull(self.hv_io.link().current_drawn), + drain_current=self.lv_io.link().current_draw.hull(self.hv_io.link().current_draw), gate_voltage=self.lv_pwr.link().voltage - self.lv_io.link().voltage, rds_on=(0, 1) * Ohm, # arbitrary ) diff --git a/edg/circuits/OpampCurrentSensor.py b/edg/circuits/OpampCurrentSensor.py index 703637557..bf6445904 100644 --- a/edg/circuits/OpampCurrentSensor.py +++ b/edg/circuits/OpampCurrentSensor.py @@ -33,7 +33,7 @@ def contents(self) -> None: self.connect(self.amp.input_positive, self.sense.sense_in) self.connect(self.amp.input_negative, self.sense.sense_out) - output_swing = self.pwr_out.link().current_drawn * self.sense.actual_resistance * self.amp.actual_ratio + output_swing = self.pwr_out.link().current_draw * self.sense.actual_resistance * self.amp.actual_ratio self.force_signal = self.Block(ForcedAnalogSignal(output_swing + self.ref.link().signal)) self.connect(self.amp.output, self.force_signal.signal_in) self.connect(self.force_signal.signal_out, self.out) diff --git a/edg/circuits/PassiveFilters.py b/edg/circuits/PassiveFilters.py index 65d663707..65bf654dc 100644 --- a/edg/circuits/PassiveFilters.py +++ b/edg/circuits/PassiveFilters.py @@ -80,7 +80,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.output = self.Port( AnalogSource(voltage_out=self.input.link().voltage, signal_out=self.input.link().signal), [Output] ) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.rc = self.Block(LowPassRc(impedance=impedance, cutoff_freq=cutoff_freq, voltage=self.input.link().voltage)) self.connect(self.input.net, self.rc.input) @@ -106,7 +106,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): ), [Output], ) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.rc = self.Block(LowPassRc(impedance=impedance, cutoff_freq=cutoff_freq, voltage=self.input.link().voltage)) self.connect(self.gnd.net, self.rc.gnd) @@ -162,7 +162,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): ), [Output], ) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.rc = self.Block(LowPassRc(impedance=impedance, cutoff_freq=cutoff_freq, voltage=self.input.link().voltage)) self.connect(self.gnd.net, self.rc.gnd) @@ -208,9 +208,9 @@ def contents(self) -> None: self.rp = self.Block(Resistor(resistance=self.impedance)) self.rn = self.Block(Resistor(resistance=self.impedance)) self.assign(self.inn.impedance, self.rn.actual_resistance + self.outn.link().sink_impedance) - self.assign(self.inn.current_draw, self.outn.link().current_drawn) + self.assign(self.inn.current_draw, self.outn.link().current_draw) self.assign(self.inp.impedance, self.rp.actual_resistance + self.outp.link().sink_impedance) - self.assign(self.inp.current_draw, self.outp.link().current_drawn) + self.assign(self.inp.current_draw, self.outp.link().current_draw) self.assign(self.outn.impedance, self.rn.actual_resistance + self.inn.link().source_impedance) self.assign(self.outp.impedance, self.rp.actual_resistance + self.inp.link().source_impedance) diff --git a/edg/circuits/PowerCircuits.py b/edg/circuits/PowerCircuits.py index c612b39ed..490eb2361 100644 --- a/edg/circuits/PowerCircuits.py +++ b/edg/circuits/PowerCircuits.py @@ -62,7 +62,7 @@ def contents(self) -> None: self.low_fet = self.Block( SwitchFet.NFet( drain_voltage=self.pwr.link().voltage, - drain_current=(0, self.out.link().current_drawn.upper()), + drain_current=(0, self.out.link().current_draw.upper()), gate_voltage=self.driver.low_out.link().voltage, rds_on=self.fet_rds, frequency=self.frequency, @@ -82,7 +82,7 @@ def contents(self) -> None: self.high_fet = self.Block( SwitchFet.NFet( drain_voltage=self.pwr.link().voltage, - drain_current=(0, self.out.link().current_drawn.upper()), + drain_current=(0, self.out.link().current_draw.upper()), gate_voltage=self.driver.high_out.link().voltage - self.driver.high_gnd.link().voltage, rds_on=self.fet_rds, frequency=self.frequency, @@ -92,7 +92,7 @@ def contents(self) -> None: self.connect( self.high_fet.drain.adapt_to( VoltageSink( - voltage_limits=self.high_fet.actual_drain_voltage_rating, current_draw=self.out.link().current_drawn + voltage_limits=self.high_fet.actual_drain_voltage_rating, current_draw=self.out.link().current_draw ) ), self.pwr, @@ -206,7 +206,7 @@ def contents(self) -> None: self.drv = self.Block( SwitchFet.PFet( drain_voltage=pwr_voltage, - drain_current=self.pwr_out.link().current_drawn, + drain_current=self.pwr_out.link().current_draw, gate_voltage=(0 * Volt(tol=0)).hull(self.target_vgs.upper()), gate_threshold_voltage=(0 * Volt(tol=0)).hull(self.target_vgs.lower()), rds_on=(0, self.max_rds), @@ -260,7 +260,7 @@ def contents(self) -> None: self.import_kicad( self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), conversions={ - "pwr_in": VoltageSink(current_draw=self.pwr_out.link().current_drawn + div_current_draw), + "pwr_in": VoltageSink(current_draw=self.pwr_out.link().current_draw + div_current_draw), "pwr_out": VoltageSource(voltage_out=self.pwr_in.link().voltage), "control": DigitalSink(), "gnd": Ground(), diff --git a/edg/circuits/PowerConditioning.py b/edg/circuits/PowerConditioning.py index ec63db165..f218c7ae5 100644 --- a/edg/circuits/PowerConditioning.py +++ b/edg/circuits/PowerConditioning.py @@ -25,7 +25,7 @@ def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: self.diode = self.Block( Diode( reverse_voltage=(0, self.pwr_in.link().voltage.upper() - self.pwr_in_diode.link().voltage.lower()), - current=self.pwr_out.link().current_drawn, + current=self.pwr_out.link().current_draw, voltage_drop=voltage_drop, ) ) @@ -34,8 +34,8 @@ def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: self.pwr_in_diode.link().voltage.upper() - self.diode.voltage_drop.lower() <= self.pwr_in.link().voltage.lower() ) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) - self.assign(self.pwr_in_diode.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) + self.assign(self.pwr_in_diode.current_draw, self.pwr_out.link().current_draw) self.connect(self.pwr_in_diode.net, self.diode.anode) self.connect(self.pwr_out.net, self.pwr_in.net, self.diode.cathode) @@ -66,11 +66,11 @@ def generate(self) -> None: self.diodes = ElementDict[Diode]() self.pwr_ins.defined() for name in requested: - pwr_in = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_drawn), name) + pwr_in = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_draw), name) self.diodes[name] = diode = self.Block( Diode( reverse_voltage=(0, self.pwr_out.voltage_out.upper() - pwr_in.link().voltage.lower()), - current=self.pwr_out.link().current_drawn, + current=self.pwr_out.link().current_draw, voltage_drop=self.voltage_drop, ) ) @@ -113,7 +113,7 @@ def contents(self) -> None: # FET behavior requires the high priority path to be higher voltage self.require(self.pwr_hi.link().voltage.lower() > self.pwr_lo.link().voltage.upper()) - output_current_draw = self.pwr_out.link().current_drawn + output_current_draw = self.pwr_out.link().current_draw self.pdr = self.Block(Resistor(10 * kOhm(tol=0.01))) self.diode = self.Block( Diode( @@ -185,7 +185,7 @@ def __init__(self, gate_resistor: RangeLike = 10 * kOhm(tol=0.05), rds_on: Range @override def contents(self) -> None: super().contents() - output_current_draw = self.pwr_out.link().current_drawn + output_current_draw = self.pwr_out.link().current_draw self.fet = self.Block( Fet.PFet( drain_voltage=(0, self.pwr_out.link().voltage.upper()), @@ -251,7 +251,7 @@ def contents(self) -> None: # use the maximum voltages and currents accounting for both directions batt_voltage = self.pwr_in.link().voltage.hull(self.pwr_out.link().reverse_voltage) - batt_current = self.pwr_out.link().current_drawn.hull(self.pwr_in.link().reverse_current_drawn) + batt_current = self.pwr_out.link().current_draw.hull(self.pwr_in.link().reverse_current_draw) power = batt_current * batt_current * self.rds_on r1_current = batt_voltage / self.r1.resistance @@ -286,7 +286,7 @@ def contents(self) -> None: "pwr_out": VoltageSource( voltage_out=batt_voltage, reverse_voltage_limits=self.pwr_in.link().reverse_voltage_limits, - reverse_current_draw=self.pwr_in.link().reverse_current_drawn, + reverse_current_draw=self.pwr_in.link().reverse_current_draw, ), "gnd": Ground(), }, @@ -341,7 +341,7 @@ def contents(self) -> None: super().contents() control_voltage = self.btn_in.link().voltage.hull(self.gnd.link().voltage) pwr_voltage = self.pwr_out.link().voltage.hull(self.gnd.link().voltage) - pwr_current = self.pwr_out.link().current_drawn.hull(RangeExpr.ZERO) + pwr_current = self.pwr_out.link().current_draw.hull(RangeExpr.ZERO) self.pull_res = self.Block(Resistor(resistance=self.pull_resistance)) self.pwr_fet = self.Block( @@ -381,7 +381,7 @@ def contents(self) -> None: self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), conversions={ "pwr_in": VoltageSink( - current_draw=self.pwr_out.link().current_drawn, + current_draw=self.pwr_out.link().current_draw, ), "pwr_out": VoltageSource( voltage_out=self.pwr_in.link().voltage, diff --git a/edg/circuits/ResistiveDivider.py b/edg/circuits/ResistiveDivider.py index 171691424..1956061ce 100644 --- a/edg/circuits/ResistiveDivider.py +++ b/edg/circuits/ResistiveDivider.py @@ -7,7 +7,7 @@ class DividerValues(ESeriesRatioValue["DividerValues"]): - """Resistive divider calculator using the ESeriesRatioUtil infrastructure. + r"""Resistive divider calculator using the ESeriesRatioUtil infrastructure. R1 is the high-side resistor, and R2 is the low-side resistor, such that Vout = Vin * R2 / (R1 + R2) @@ -184,7 +184,7 @@ def __init__(self, impedance: RangeLike) -> None: self.connect(self.input.net, self.div.top) self.connect(self.output.net, self.div.center) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.actual_rtop = self.Parameter(RangeExpr(self.div.actual_rtop)) self.actual_rbot = self.Parameter(RangeExpr(self.div.actual_rbot)) @@ -275,7 +275,7 @@ def __init__(self, ratio: RangeLike, impedance: RangeLike) -> None: AnalogSource(voltage_out=output_voltage, signal_out=output_voltage, impedance=self.div.actual_impedance), [Output], ) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) self.connect(self.gnd.net, self.div.bottom) self.connect(self.output.net, self.div.center) self.connect(self.input.net, self.div.top) diff --git a/edg/circuits/ResistiveSensor.py b/edg/circuits/ResistiveSensor.py index 755ea4cba..30ab909ee 100644 --- a/edg/circuits/ResistiveSensor.py +++ b/edg/circuits/ResistiveSensor.py @@ -31,7 +31,7 @@ def contents(self) -> None: self.top = self.Block(Resistor(self.fixed_resistance, voltage=self.input.link().voltage)) self.bot = self.Block(PassiveConnector(2)) self.connect(self.input.net, self.top.a) - self.assign(self.input.current_draw, self.output.link().current_drawn) + self.assign(self.input.current_draw, self.output.link().current_draw) output_voltage = ResistiveDivider.divider_output( self.input.link().voltage, self.gnd.link().voltage, self.actual_ratio ) diff --git a/edg/circuits/SwitchMatrix.py b/edg/circuits/SwitchMatrix.py index 07d717098..f2b63ce25 100644 --- a/edg/circuits/SwitchMatrix.py +++ b/edg/circuits/SwitchMatrix.py @@ -37,11 +37,11 @@ def contents(self) -> None: self.row.init_from(DigitalSink()) # switch common, externally driven for column scan, assumed ideal self.sw = self.Block( - Switch(voltage=self.col.link().voltage - self.row.link().voltage, current=self.col.link().current_drawn) + Switch(voltage=self.col.link().voltage - self.row.link().voltage, current=self.col.link().current_draw) ) self.d = self.Block( Diode( - current=self.col.link().current_drawn, + current=self.col.link().current_draw, reverse_voltage=(self.col.link().voltage - self.row.link().voltage).abs(), voltage_drop=self.voltage_drop, ) diff --git a/edg/circuits/UsbBitBang.py b/edg/circuits/UsbBitBang.py index bac624bd4..f75b5cc51 100644 --- a/edg/circuits/UsbBitBang.py +++ b/edg/circuits/UsbBitBang.py @@ -19,7 +19,7 @@ def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir: TODO: unify code w/ DigitalBidir bridge?""" return DigitalBidir( voltage_out=link_port.link().voltage, - current_draw=link_port.link().current_drawn, + current_draw=link_port.link().current_draw, voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits, output_thresholds=link_port.link().output_thresholds, diff --git a/edg/circuits/VoltageClamping.py b/edg/circuits/VoltageClamping.py index c8565a738..2615d8c80 100644 --- a/edg/circuits/VoltageClamping.py +++ b/edg/circuits/VoltageClamping.py @@ -103,7 +103,7 @@ def contents(self) -> None: super().contents() # TODO bidirectional clamping calcs? - self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn) + self.assign(self.signal_in.current_draw, self.signal_out.link().current_draw) self.res = self.Block( Resistor( resistance=1 diff --git a/edg/electronics_interfaces/AnalogPort.py b/edg/electronics_interfaces/AnalogPort.py index eb7643056..dadde1072 100644 --- a/edg/electronics_interfaces/AnalogPort.py +++ b/edg/electronics_interfaces/AnalogPort.py @@ -1,6 +1,8 @@ from __future__ import annotations from typing import Optional, Tuple + +from deprecated import deprecated from typing_extensions import override from ..electronics_model import * @@ -22,7 +24,7 @@ def __init__(self) -> None: self.voltage = self.Parameter(RangeExpr(self.source.voltage_out)) self.signal = self.Parameter(RangeExpr(self.source.signal_out)) - self.current_drawn = self.Parameter(RangeExpr()) + self.current_draw = self.Parameter(RangeExpr()) self.voltage_limits = self.Parameter(RangeExpr()) self.signal_limits = self.Parameter(RangeExpr()) @@ -40,7 +42,7 @@ def contents(self) -> None: " of limits: ", DescriptionString.FormatUnits(self.voltage_limits, "V"), "\ncurrent: ", - DescriptionString.FormatUnits(self.current_drawn, "A"), + DescriptionString.FormatUnits(self.current_draw, "A"), " of limits: ", DescriptionString.FormatUnits(self.current_limits, "A"), "\nsink impedance: ", @@ -53,7 +55,7 @@ def contents(self) -> None: self.require( self.source.impedance.upper() <= self.sink_impedance.lower() * 0.1 ) # about 10x for signal integrity - self.assign(self.current_drawn, self.sinks.sum(lambda x: x.current_draw)) + self.assign(self.current_draw, self.sinks.sum(lambda x: x.current_draw)) self.assign(self.voltage_limits, self.sinks.intersection(lambda x: x.voltage_limits)) self.require(self.voltage_limits.contains(self.voltage), "incompatible voltage levels") @@ -61,7 +63,12 @@ def contents(self) -> None: self.require(self.voltage.contains(self.signal), "signal levels not contained within voltage") self.require(self.signal_limits.contains(self.signal), "incompatible signal levels") self.assign(self.current_limits, self.source.current_limits) - self.require(self.current_limits.contains(self.current_drawn), "overcurrent") + self.require(self.current_limits.contains(self.current_draw), "overcurrent") + + @property + @deprecated(f"Use current_draw") + def current_drawn(self) -> RangeExpr: + return self.current_draw class AnalogBase(Port[AnalogLink]): @@ -95,7 +102,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) self.assign(self.outer_port.impedance, self.inner_link.link().sink_impedance) - self.assign(self.outer_port.current_draw, self.inner_link.link().current_drawn) + self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) self.assign(self.outer_port.signal_limits, self.inner_link.link().signal_limits) @@ -137,7 +144,7 @@ def contents(self) -> None: self.outer_port.current_limits, self.inner_link.link().current_limits ) # TODO compensate for internal current draw - self.assign(self.inner_link.current_draw, self.outer_port.link().current_drawn) + self.assign(self.inner_link.current_draw, self.outer_port.link().current_draw) self.assign(self.inner_link.impedance, self.outer_port.link().sink_impedance) @@ -213,7 +220,7 @@ def __init__(self) -> None: voltage_out=(self.src.link().voltage.upper(), self.src.link().voltage.upper()), ) ) - self.assign(self.src.current_draw, self.dst.link().current_drawn) + self.assign(self.src.current_draw, self.dst.link().current_draw) self.connect(self.src.net, self.dst.net) diff --git a/edg/electronics_interfaces/CircuitPackingBlock.py b/edg/electronics_interfaces/CircuitPackingBlock.py index 2562c63a5..3980fcc01 100644 --- a/edg/electronics_interfaces/CircuitPackingBlock.py +++ b/edg/electronics_interfaces/CircuitPackingBlock.py @@ -78,7 +78,7 @@ def generate(self) -> None: self.pwr_ins.defined() for in_request in self.get(self.pwr_ins.requested()): in_port = self.pwr_ins.append_elt( - VoltageSink(current_draw=self.pwr_out.link().current_drawn / len(self.get(self.pwr_ins.requested()))), + VoltageSink(current_draw=self.pwr_out.link().current_draw / len(self.get(self.pwr_ins.requested()))), in_request, ) self.connect(in_port.net, self.packed.elts.request(in_request)) diff --git a/edg/electronics_interfaces/DigitalPorts.py b/edg/electronics_interfaces/DigitalPorts.py index f2148de89..ccfbcec64 100644 --- a/edg/electronics_interfaces/DigitalPorts.py +++ b/edg/electronics_interfaces/DigitalPorts.py @@ -38,7 +38,7 @@ def __init__(self) -> None: self.voltage = self.Parameter(RangeExpr()) self.voltage_limits = self.Parameter(RangeExpr()) - self.current_drawn = self.Parameter(RangeExpr()) + self.current_draw = self.Parameter(RangeExpr()) self.current_limits = self.Parameter(RangeExpr()) self.output_thresholds = self.Parameter(RangeExpr()) @@ -68,7 +68,7 @@ def contents(self) -> None: " of limits: ", DescriptionString.FormatUnits(self.voltage_limits, "V"), "\ncurrent: ", - DescriptionString.FormatUnits(self.current_drawn, "A"), + DescriptionString.FormatUnits(self.current_draw, "A"), " of limits: ", DescriptionString.FormatUnits(self.current_limits, "A"), "\noutput thresholds: ", @@ -93,7 +93,7 @@ def contents(self) -> None: self.require(self.voltage_limits.contains(self.voltage), "overvoltage") self.assign( - self.current_drawn, self.sinks.sum(lambda x: x.current_draw) + self.bidirs.sum(lambda x: x.current_draw) + self.current_draw, self.sinks.sum(lambda x: x.current_draw) + self.bidirs.sum(lambda x: x.current_draw) ) self.assign( self.current_limits, @@ -101,7 +101,7 @@ def contents(self) -> None: self.bidirs.intersection(lambda x: x.current_limits) ), ) - self.require(self.current_limits.contains(self.current_drawn), "overcurrent") + self.require(self.current_limits.contains(self.current_draw), "overcurrent") self.assign( self.output_thresholds, @@ -161,6 +161,11 @@ def contents(self) -> None: "conflicting source drivers", ) + @property + @deprecated(f"Use current_draw") + def current_drawn(self) -> RangeExpr: + return self.current_draw + class DigitalBase(Port[DigitalLink]): link_type = DigitalLink @@ -192,7 +197,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) - self.assign(self.outer_port.current_draw, self.inner_link.link().current_drawn) + self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.input_thresholds, self.inner_link.link().input_thresholds) self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) @@ -312,8 +317,8 @@ def contents(self) -> None: self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits - ) # TODO subtract internal current drawn - self.assign(self.inner_link.current_draw, self.outer_port.link().current_drawn) + ) # TODO subtract internal current draw + self.assign(self.inner_link.current_draw, self.outer_port.link().current_draw) self.assign(self.outer_port.output_thresholds, self.inner_link.link().output_thresholds) @@ -325,7 +330,7 @@ def __init__(self) -> None: self.dst = self.Port( VoltageSource(voltage_out=(self.src.link().output_thresholds.upper(), self.src.link().voltage.upper())) ) - self.assign(self.src.current_draw, self.dst.link().current_drawn) + self.assign(self.src.current_draw, self.dst.link().current_draw) self.connect(self.src.net, self.dst.net) @@ -486,7 +491,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) - self.assign(self.outer_port.current_draw, self.inner_link.link().current_drawn) + self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits diff --git a/edg/electronics_interfaces/DummyDevices.py b/edg/electronics_interfaces/DummyDevices.py index d90b0679c..6dbb3cf7e 100644 --- a/edg/electronics_interfaces/DummyDevices.py +++ b/edg/electronics_interfaces/DummyDevices.py @@ -98,7 +98,7 @@ def __init__(self, forced_current_limit: RangeLike) -> None: ) self.connect(self.pwr_in.net, self.pwr_out.net) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) class ForcedVoltage(DummyDevice): @@ -112,7 +112,7 @@ def __init__(self, forced_voltage: RangeLike) -> None: self.pwr_out = self.Port(VoltageSource(voltage_out=forced_voltage), [Output]) self.connect(self.pwr_in.net, self.pwr_out.net) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) class ForcedVoltageCurrent(DummyDevice): @@ -141,7 +141,7 @@ def __init__(self, forced_signal: RangeLike = RangeExpr()) -> None: [Output], ) - self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn) + self.assign(self.signal_in.current_draw, self.signal_out.link().current_draw) self.connect(self.signal_in.net, self.signal_out.net) @override diff --git a/edg/electronics_interfaces/MergedBlocks.py b/edg/electronics_interfaces/MergedBlocks.py index 9cb6566fb..8e2b1e093 100644 --- a/edg/electronics_interfaces/MergedBlocks.py +++ b/edg/electronics_interfaces/MergedBlocks.py @@ -21,7 +21,7 @@ def generate(self) -> None: super().generate() self.pwr_ins.defined() for in_request in self.get(self.pwr_ins.requested()): - elt_port = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_drawn), in_request) + elt_port = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_draw), in_request) self.connect(self.pwr_out.net, elt_port.net) self.assign(self.pwr_out.voltage_out, self.pwr_ins.hull(lambda x: x.link().voltage)) @@ -52,7 +52,7 @@ def generate(self) -> None: super().generate() self.ins.defined() for in_request in self.get(self.ins.requested()): - elt_port = self.ins.append_elt(DigitalSink(current_draw=self.out.link().current_drawn), in_request) + elt_port = self.ins.append_elt(DigitalSink(current_draw=self.out.link().current_draw), in_request) self.connect(self.out.net, elt_port.net) self.assign(self.out.voltage_out, self.ins.hull(lambda x: x.link().voltage)) @@ -87,7 +87,7 @@ def generate(self) -> None: self.inputs.defined() for in_request in self.get(self.inputs.requested()): elt_port = self.inputs.append_elt( - AnalogSink(current_draw=self.output.link().current_drawn, impedance=self.output.link().sink_impedance), + AnalogSink(current_draw=self.output.link().current_draw, impedance=self.output.link().sink_impedance), in_request, ) self.connect(self.output.net, elt_port.net) diff --git a/edg/electronics_interfaces/VoltageDummy.py b/edg/electronics_interfaces/VoltageDummy.py index d55150874..d7b8fbfb8 100644 --- a/edg/electronics_interfaces/VoltageDummy.py +++ b/edg/electronics_interfaces/VoltageDummy.py @@ -25,7 +25,7 @@ def __init__( [Power, InOut], ) - self.current_drawn = self.Parameter(RangeExpr(self.io.link().current_drawn)) + self.current_draw = self.Parameter(RangeExpr(self.io.link().current_draw)) self.voltage_limits = self.Parameter(RangeExpr(self.io.link().voltage_limits)) self.reverse_voltage = self.Parameter(RangeExpr(self.io.link().reverse_voltage)) @@ -34,6 +34,11 @@ def __init__( def pwr(self) -> VoltageSource: return self.io + @property + @deprecated(f"Use current_draw") + def current_drawn(self) -> RangeExpr: + return self.current_draw + class DummyVoltageSink(BaseDummyBlock[VoltageLink]): diff --git a/edg/electronics_interfaces/VoltagePorts.py b/edg/electronics_interfaces/VoltagePorts.py index 34197a923..21a7528de 100644 --- a/edg/electronics_interfaces/VoltagePorts.py +++ b/edg/electronics_interfaces/VoltagePorts.py @@ -1,6 +1,8 @@ from __future__ import annotations from typing import * + +from deprecated import deprecated from typing_extensions import override from ..electronics_model import * @@ -35,12 +37,12 @@ def __init__(self) -> None: self.voltage = self.Parameter(RangeExpr()) self.voltage_limits = self.Parameter(RangeExpr()) - self.current_drawn = self.Parameter(RangeExpr()) + self.current_draw = self.Parameter(RangeExpr()) self.current_limits = self.Parameter(RangeExpr()) self.reverse_voltage = self.Parameter(RangeExpr()) self.reverse_voltage_limits = self.Parameter(RangeExpr()) - self.reverse_current_drawn = self.Parameter(RangeExpr()) + self.reverse_current_draw = self.Parameter(RangeExpr()) self.reverse_current_limits = self.Parameter(RangeExpr()) @override @@ -53,7 +55,7 @@ def contents(self) -> None: " of limits: ", DescriptionString.FormatUnits(self.voltage_limits, "V"), "\ncurrent: ", - DescriptionString.FormatUnits(self.current_drawn, "A"), + DescriptionString.FormatUnits(self.current_draw, "A"), " of limits: ", DescriptionString.FormatUnits(self.current_limits, "A"), ) @@ -64,8 +66,8 @@ def contents(self) -> None: self.assign(self.voltage_limits, self.sinks.intersection(lambda x: x.voltage_limits)) self.require(self.voltage_limits.contains(self.voltage), "voltage out of limits") self.assign(self.current_limits, self.source.current_limits) - self.assign(self.current_drawn, self.sinks.sum(lambda x: x.current_draw)) - self.require(self.current_limits.contains(self.current_drawn), "current draw out of limits") + self.assign(self.current_draw, self.sinks.sum(lambda x: x.current_draw)) + self.require(self.current_limits.contains(self.current_draw), "current draw out of limits") has_reverse_voltage = self.reverse_voltage != RangeExpr.EMPTY self.assign(self.reverse_voltage, self.sinks.hull(lambda x: x.reverse_voltage_out)) @@ -93,13 +95,23 @@ def contents(self) -> None: "voltage out of range of reverse voltage limits", ) - self.assign(self.reverse_current_drawn, self.source.reverse_current_draw) + self.assign(self.reverse_current_draw, self.source.reverse_current_draw) self.assign(self.reverse_current_limits, self.sinks.hull(lambda x: x.reverse_current_limits)) self.require( - has_reverse_voltage.implies(self.reverse_current_limits.contains(self.reverse_current_drawn)), + has_reverse_voltage.implies(self.reverse_current_limits.contains(self.reverse_current_draw)), "reverse current out of limits", ) + @property + @deprecated(f"Use current_draw") + def current_drawn(self) -> RangeExpr: + return self.current_draw + + @property + @deprecated(f"Use reverse_current_draw") + def reverse_current_drawn(self) -> RangeExpr: + return self.reverse_current_draw + class VoltageSinkBridge(PortBridge): def __init__(self) -> None: @@ -133,14 +145,14 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.outer_port.current_draw, self.inner_link.link().current_drawn) + self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) self.assign(self.outer_port.reverse_voltage_out, self.inner_link.link().reverse_voltage) self.assign(self.outer_port.reverse_current_limits, self.inner_link.link().reverse_current_limits) self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) self.assign(self.inner_link.reverse_voltage_limits, self.outer_port.link().reverse_voltage_limits) - self.assign(self.inner_link.reverse_current_draw, self.outer_port.link().reverse_current_drawn) + self.assign(self.inner_link.reverse_current_draw, self.outer_port.link().reverse_current_draw) class VoltageSourceBridge(PortBridge): # basic passthrough port, sources look the same inside and outside @@ -177,11 +189,11 @@ def contents(self) -> None: self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits - ) # TODO adjust for inner current drawn + ) # TODO adjust for inner current draw self.assign(self.outer_port.reverse_voltage_limits, self.inner_link.link().reverse_voltage_limits) - self.assign(self.outer_port.reverse_current_draw, self.inner_link.link().reverse_current_drawn) + self.assign(self.outer_port.reverse_current_draw, self.inner_link.link().reverse_current_draw) - self.assign(self.inner_link.current_draw, self.outer_port.link().current_drawn) + self.assign(self.inner_link.current_draw, self.outer_port.link().current_draw) self.assign(self.inner_link.reverse_voltage_out, self.outer_port.link().reverse_voltage) @@ -192,7 +204,7 @@ class VoltageBase(Port[VoltageLink]): # these are here (instead of in VoltageSource) since the port may be on the other side of a bridge def as_ground(self, current_draw: RangeLike = RangeExpr.ZERO) -> GroundReference: - """Adapts this port to a ground. Current draw is the current drawn from this port, and is required + """Adapts this port to a ground. Current draw is the current draw from this port, and is required since ground does not model current draw. """ return self._convert(VoltageSinkAdapterGroundReference(current_draw)) @@ -253,7 +265,7 @@ def __init__(self) -> None: output_thresholds=(FloatExpr._to_expr_type(-float("inf")), self.src.link().voltage.upper()), ) ) - self.assign(self.src.current_draw, self.dst.link().current_drawn) # TODO might be an overestimate + self.assign(self.src.current_draw, self.dst.link().current_draw) # TODO might be an overestimate self.connect(self.dst.net, self.src.net) @@ -271,7 +283,7 @@ def __init__(self) -> None: impedance=(0, 0) * Ohm, # TODO not actually true, but pretty darn low? ) ) - self.assign(self.src.current_draw, self.dst.link().current_drawn) + self.assign(self.src.current_draw, self.dst.link().current_draw) self.connect(self.dst.net, self.src.net) diff --git a/edg/parts/microcontroller/Rp2040.py b/edg/parts/microcontroller/Rp2040.py index 8a4282a4b..88cf58fae 100644 --- a/edg/parts/microcontroller/Rp2040.py +++ b/edg/parts/microcontroller/Rp2040.py @@ -85,7 +85,7 @@ def __init__(self, **kwargs: Any) -> None: VoltageSink( voltage_limits=(1.62, 3.63) * Volt, # Table 628 current_draw=self.vreg_vout.is_connected().then_else( - self.vreg_vout.link().current_drawn, 0 * Amp(tol=0) + self.vreg_vout.link().current_draw, 0 * Amp(tol=0) ), ) ) @@ -459,7 +459,7 @@ def generate(self) -> None: VoltageSink( # based on RS3236-3.3 voltage_limits=(3.3 * 1.025 + 0.55, 7.5) * Volt, # output * tolerance + dropout @ 300mA current_draw=self.pwr_out.is_connected().then_else( # prop output current draw - self.pwr_out.link().current_drawn, (0, 0) * Amp + self.pwr_out.link().current_draw, (0, 0) * Amp ), ) ) diff --git a/edg/parts/power/Batteries.py b/edg/parts/power/Batteries.py index 3e9282c07..1a6584cd1 100644 --- a/edg/parts/power/Batteries.py +++ b/edg/parts/power/Batteries.py @@ -134,7 +134,7 @@ def generate(self) -> None: if prev_cell is None: # first cell, direct connect to gnd self.connect(self.gnd, cell.gnd) else: - self.connect(prev_cell.pwr.as_ground(self.pwr.link().current_drawn), cell.gnd) + self.connect(prev_cell.pwr.as_ground(self.pwr.link().current_draw), cell.gnd) prev_capacity_min = cell.actual_capacity.lower().min(prev_capacity_min) prev_capacity_max = cell.actual_capacity.upper().min(prev_capacity_max) prev_cell = cell diff --git a/edg/parts/power/BatteryProtector_S8261A.py b/edg/parts/power/BatteryProtector_S8261A.py index feef25330..b189a45ef 100644 --- a/edg/parts/power/BatteryProtector_S8261A.py +++ b/edg/parts/power/BatteryProtector_S8261A.py @@ -55,7 +55,7 @@ def __init__(self) -> None: self.do_fet = self.Block( Fet.NFet( - drain_current=self.pwr_in.link().current_drawn, + drain_current=self.pwr_in.link().current_draw, gate_voltage=self.pwr_in.link().voltage, rds_on=(0, 0.1) * Ohm, drain_voltage=self.pwr_in.link().voltage, @@ -63,7 +63,7 @@ def __init__(self) -> None: ) self.co_fet = self.Block( Fet.NFet( - drain_current=self.pwr_in.link().current_drawn, + drain_current=self.pwr_in.link().current_draw, gate_voltage=self.pwr_in.link().voltage, rds_on=(0, 0.1) * Ohm, drain_voltage=self.pwr_in.link().voltage, diff --git a/edg/parts/power/converter/AnalogDevices_Boost.py b/edg/parts/power/converter/AnalogDevices_Boost.py index bf74ae302..83b2878b3 100644 --- a/edg/parts/power/converter/AnalogDevices_Boost.py +++ b/edg/parts/power/converter/AnalogDevices_Boost.py @@ -83,7 +83,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, self.NMOS_CURRENT_LIMIT) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/converter/Ap3418.py b/edg/parts/power/converter/Ap3418.py index 694a89fe5..858ea28de 100644 --- a/edg/parts/power/converter/Ap3418.py +++ b/edg/parts/power/converter/Ap3418.py @@ -11,7 +11,7 @@ def __init__(self) -> None: self.sw = self.Port(VoltageSource()) # internal switch specs not defined, only bulk current limit defined self.pwr_in = self.Port( VoltageSink( - voltage_limits=(2.5, 5.5) * Volt, current_draw=self.sw.link().current_drawn # TODO quiescent current + voltage_limits=(2.5, 5.5) * Volt, current_draw=self.sw.link().current_draw # TODO quiescent current ), [Power], ) @@ -81,7 +81,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 1.8) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/converter/CustomBuck.py b/edg/parts/power/converter/CustomBuck.py index 9286f5a30..5e97faf08 100644 --- a/edg/parts/power/converter/CustomBuck.py +++ b/edg/parts/power/converter/CustomBuck.py @@ -39,7 +39,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.output_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, Range.exact(0), input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, @@ -52,7 +52,7 @@ def contents(self) -> None: self.sw = self.Block(FetHalfBridge(frequency=self.frequency, fet_rds=self.rds_on)) self.connect(self.sw.gnd, self.gnd) (self.pwr_in_force,), _ = self.chain( # use average current draw for boundary ports - self.pwr_in, self.Block(ForcedVoltageCurrentDraw(self.power_path.switch.link().current_drawn)), self.sw.pwr + self.pwr_in, self.Block(ForcedVoltageCurrentDraw(self.power_path.switch.link().current_draw)), self.sw.pwr ) self.connect(self.sw.pwr_logic, self.pwr_logic) sw_ctl = self.sw.with_mixin(HalfBridgeIndependent()) diff --git a/edg/parts/power/converter/CustomBuckBoost.py b/edg/parts/power/converter/CustomBuckBoost.py index eabcc2c9a..a9e98eb0f 100644 --- a/edg/parts/power/converter/CustomBuckBoost.py +++ b/edg/parts/power/converter/CustomBuckBoost.py @@ -68,7 +68,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.output_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, Range.exact(0), input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/converter/DiodesInc_Boost.py b/edg/parts/power/converter/DiodesInc_Boost.py index c2c67f208..9efa8dee6 100644 --- a/edg/parts/power/converter/DiodesInc_Boost.py +++ b/edg/parts/power/converter/DiodesInc_Boost.py @@ -79,7 +79,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 0.5) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, @@ -91,7 +91,7 @@ def contents(self) -> None: self.rect = self.Block( Diode( reverse_voltage=(0, self.pwr_out.voltage_out.upper()), - current=self.pwr_out.link().current_drawn, + current=self.pwr_out.link().current_draw, voltage_drop=(0, 0.4) * Volt, reverse_recovery_time=(0, 500) * nSecond, # guess from Digikey's classification for "fast recovery" ) diff --git a/edg/parts/power/converter/Mp2722.py b/edg/parts/power/converter/Mp2722.py index 05ff11615..baec464c2 100644 --- a/edg/parts/power/converter/Mp2722.py +++ b/edg/parts/power/converter/Mp2722.py @@ -22,7 +22,7 @@ def __init__(self, charging_current: RangeLike): voltage_out=self.vin.link().voltage.hull(self.gnd.link().voltage), current_limits=(0, 5) * Amp ) # up to 5A charge / system current ) # internal switch specs not defined, only bulk current limit defined - self.assign(self.vin.current_draw, self.sw.link().current_drawn) # TODO quiescent current + self.assign(self.vin.current_draw, self.sw.link().current_draw) # TODO quiescent current self.pmid = self.Port( VoltageSource( @@ -47,7 +47,7 @@ def __init__(self, charging_current: RangeLike): self.batt = self.Port( VoltageSink( # technically bidir voltage_limits=(2.6, 4.6) * Volt, # 2.6 is max UV threshold - current_draw=self.sys.link().current_drawn, # TODO model (reverse) charging current + current_draw=self.sys.link().current_draw, # TODO model (reverse) charging current ) ) self.battsns = self.Port(VoltageSink()) # technically analog input @@ -187,7 +187,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, vsys_range, self.actual_frequency, - self.pwr_out.link().current_drawn + self.ic.sys.link().current_drawn, + self.pwr_out.link().current_draw + self.ic.sys.link().current_draw, (0, 3.2) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/converter/TexasInstruments_Boost.py b/edg/parts/power/converter/TexasInstruments_Boost.py index 7c0e31637..73882b0b2 100644 --- a/edg/parts/power/converter/TexasInstruments_Boost.py +++ b/edg/parts/power/converter/TexasInstruments_Boost.py @@ -83,7 +83,7 @@ def contents(self) -> None: # and has different component sizing guidelines vin = self.pwr_in.link().voltage vout = self.pwr_out.link().voltage - iload = self.pwr_out.link().current_drawn + iload = self.pwr_out.link().current_draw efficiency_est = Range(0.7, 0.85) # given by datasheet ilim = (350, 450) * mAmp # current limit determined by chip @@ -118,7 +118,7 @@ def contents(self) -> None: self.inductor.a.adapt_to( VoltageSink( voltage_limits=RangeExpr.ALL, - current_draw=self.pwr_out.link().current_drawn + current_draw=self.pwr_out.link().current_draw * self.pwr_out.link().voltage / self.pwr_in.link().voltage, ) @@ -253,7 +253,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 1) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, @@ -271,7 +271,7 @@ def contents(self) -> None: self.rect = self.Block( Diode( reverse_voltage=(0, self.pwr_out.voltage_out.upper()), - current=self.pwr_out.link().current_drawn, + current=self.pwr_out.link().current_draw, voltage_drop=(0, 0.8) * Volt, reverse_recovery_time=(0, 500) * nSecond, # guess from Digikey's classification for "fast recovery" ) diff --git a/edg/parts/power/converter/TexasInstruments_Buck.py b/edg/parts/power/converter/TexasInstruments_Buck.py index aba833b4c..b1320dd6b 100644 --- a/edg/parts/power/converter/TexasInstruments_Buck.py +++ b/edg/parts/power/converter/TexasInstruments_Buck.py @@ -25,7 +25,7 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - self.assign(self.pwr_in.current_draw, self.sw.link().current_drawn) # TODO quiescent current + self.assign(self.pwr_in.current_draw, self.sw.link().current_draw) # TODO quiescent current self.footprint( "U", "Package_TO_SOT_SMD:SOT-23-6", @@ -87,7 +87,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 1.2) * Amp, # output current limit, switch limit not given input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, @@ -116,7 +116,7 @@ def __init__(self) -> None: current_limits=(0, 2) * Amp, # most conservative figures, low-side limited. TODO: better ones? ) ) # internal switch specs not defined, only bulk current limit defined - self.assign(self.pwr_in.current_draw, self.sw.link().current_drawn) # TODO quiescent current) + self.assign(self.pwr_in.current_draw, self.sw.link().current_draw) # TODO quiescent current) self.fb = self.Port(AnalogSink()) # no impedance specs self.boot = self.Port( @@ -197,7 +197,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 2.5) * Amp, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, @@ -250,9 +250,7 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - self.assign( - self.vin.current_draw, self.sw.link().current_drawn + (3, 40) * uAmp - ) # shutdown to non-switching Iq + self.assign(self.vin.current_draw, self.sw.link().current_draw + (3, 40) * uAmp) # shutdown to non-switching Iq self.footprint( "U", "Package_SO:HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias", @@ -333,7 +331,7 @@ def generate(self) -> None: self.pwr_in.link().voltage, self.fb.actual_input_voltage, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, (0, 1.8) * Amp, # low-side min switch current limit input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/converter/TexasInstruments_SwitchedCap.py b/edg/parts/power/converter/TexasInstruments_SwitchedCap.py index 419145972..b6bc2f632 100644 --- a/edg/parts/power/converter/TexasInstruments_SwitchedCap.py +++ b/edg/parts/power/converter/TexasInstruments_SwitchedCap.py @@ -16,7 +16,7 @@ def __init__(self) -> None: self.capn = self.Port(Passive()) self.capp = self.Port(Passive()) self.out = self.Port(VoltageSource(voltage_out=-self.vp.link().voltage, current_limits=(0, 40) * mAmp)) - self.assign(self.vp.current_draw, (1, 500) * uAmp + self.out.link().current_drawn) + self.assign(self.vp.current_draw, (1, 500) * uAmp + self.out.link().current_draw) # self.sd = self.Port(DigitalSink.from_supply( # self.gnd, self.vp, @@ -81,7 +81,7 @@ def contents(self) -> None: self.cout = self.Block( DecouplingCapacitor( ( - self.pwr_out.link().current_drawn.upper() / self.ic.FREQUENCY.lower / self.output_ripple_limit, + self.pwr_out.link().current_draw.upper() / self.ic.FREQUENCY.lower / self.output_ripple_limit, float("inf"), ) ) diff --git a/edg/parts/power/converter/Torex_Boost.py b/edg/parts/power/converter/Torex_Boost.py index 2fcc6934d..20ff6fbe8 100644 --- a/edg/parts/power/converter/Torex_Boost.py +++ b/edg/parts/power/converter/Torex_Boost.py @@ -107,7 +107,7 @@ def contents(self) -> None: self.pwr_in.link().voltage, self.ic.vout.voltage_out, self.actual_frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, self.ic.actual_current_limit, input_voltage_ripple=self.input_ripple_limit, output_voltage_ripple=self.output_ripple_limit, diff --git a/edg/parts/power/gate_driver/Ir2301.py b/edg/parts/power/gate_driver/Ir2301.py index 5fbbd7212..1fb03dd1a 100644 --- a/edg/parts/power/gate_driver/Ir2301.py +++ b/edg/parts/power/gate_driver/Ir2301.py @@ -28,7 +28,7 @@ def __init__(self) -> None: self.com, self.vcc, current_limits=(-250, 120) * mAmp ) # static electrical characteristics: output short circuit pulsed current ) - self.assign(self.vcc.current_draw, (50, 190) * uAmp + self.lo.link().current_drawn) + self.assign(self.vcc.current_draw, (50, 190) * uAmp + self.lo.link().current_draw) self.vs = self.Port( Ground.from_gnd(self.com, voltage_limits=(-5, 600)) # no current draw since this is a "ground" pin @@ -42,7 +42,7 @@ def __init__(self) -> None: * mAmp, # static electrical characteristics: output short circuit pulsed current ) ) - self.assign(self.vb.current_draw, (50, 190) * uAmp + self.ho.link().current_drawn) + self.assign(self.vb.current_draw, (50, 190) * uAmp + self.ho.link().current_draw) @override def contents(self) -> None: diff --git a/edg/parts/power/gate_driver/Ncp3420.py b/edg/parts/power/gate_driver/Ncp3420.py index c1aa2b25e..a0ddba49a 100644 --- a/edg/parts/power/gate_driver/Ncp3420.py +++ b/edg/parts/power/gate_driver/Ncp3420.py @@ -50,7 +50,7 @@ def __init__(self) -> None: ) self.assign( - self.vcc.current_draw, (0.7, 5.0) * mAmp + self.drvl.link().current_drawn + self.drvh.link().current_drawn + self.vcc.current_draw, (0.7, 5.0) * mAmp + self.drvl.link().current_draw + self.drvh.link().current_draw ) # only system supply given @override diff --git a/edg/parts/power/gate_driver/Ucc27282.py b/edg/parts/power/gate_driver/Ucc27282.py index e4eb28c19..0e75bde07 100644 --- a/edg/parts/power/gate_driver/Ucc27282.py +++ b/edg/parts/power/gate_driver/Ucc27282.py @@ -43,7 +43,7 @@ def __init__(self) -> None: # quiescent to operating, vdd and hb, plus output draw self.assign( self.vdd.current_draw, - (0.3, 4.5) * mAmp + (0.2, 4) * mAmp + self.lo.link().current_drawn + self.ho.link().current_drawn, + (0.3, 4.5) * mAmp + (0.2, 4) * mAmp + self.lo.link().current_draw + self.ho.link().current_draw, ) @override diff --git a/edg/parts/power/motor/Bldc_Drv8313.py b/edg/parts/power/motor/Bldc_Drv8313.py index d033b7824..0ab90662c 100644 --- a/edg/parts/power/motor/Bldc_Drv8313.py +++ b/edg/parts/power/motor/Bldc_Drv8313.py @@ -60,7 +60,7 @@ def contents(self) -> None: self.pgnds.append_elt(Passive(), i) self.require(out_i.is_connected().implies(en_i.is_connected() & in_i.is_connected())) - channel_currents.append(out_i.is_connected().then_else(out_i.link().current_drawn.abs().upper(), 0 * mAmp)) + channel_currents.append(out_i.is_connected().then_else(out_i.link().current_draw.abs().upper(), 0 * mAmp)) out_connected.append(out_i.is_connected()) overall_current = functools.reduce(lambda a, b: a.max(b), channel_currents) @@ -167,7 +167,7 @@ def generate(self) -> None: gnd_voltage_source = self.gnd.as_voltage_source() res = self.pgnd_res[i] = self.Block( CurrentSenseResistor(resistance=self.risense_res, sense_in_reqd=False) - ).connected(gnd_voltage_source, pgnd_pin.adapt_to(VoltageSink(current_draw=out.link().current_drawn))) + ).connected(gnd_voltage_source, pgnd_pin.adapt_to(VoltageSink(current_draw=out.link().current_draw))) self.connect(self.pgnd_sense.append_elt(AnalogSource.empty(), i), res.sense_out) else: self.connect(pgnd_pin.adapt_to(Ground()), self.gnd) diff --git a/edg/parts/power/motor/MotorDriver_Drv8833.py b/edg/parts/power/motor/MotorDriver_Drv8833.py index dfa2dc622..909570132 100644 --- a/edg/parts/power/motor/MotorDriver_Drv8833.py +++ b/edg/parts/power/motor/MotorDriver_Drv8833.py @@ -50,11 +50,11 @@ def contents(self) -> None: + ( 0, # calculate possible motor current, assuming A1/2 and B1/2 are coupled (and not independent) self.aout1.is_connected() - .then_else(self.aout1.link().current_drawn.abs().upper(), 0 * mAmp) - .max(self.aout2.is_connected().then_else(self.aout2.link().current_drawn.abs().upper(), 0 * mAmp)) + .then_else(self.aout1.link().current_draw.abs().upper(), 0 * mAmp) + .max(self.aout2.is_connected().then_else(self.aout2.link().current_draw.abs().upper(), 0 * mAmp)) + self.bout1.is_connected() - .then_else(self.bout1.link().current_drawn.abs().upper(), 0 * mAmp) - .max(self.bout2.is_connected().then_else(self.bout2.link().current_drawn.abs().upper(), 0 * mAmp)), + .then_else(self.bout1.link().current_draw.abs().upper(), 0 * mAmp) + .max(self.bout2.is_connected().then_else(self.bout2.link().current_draw.abs().upper(), 0 * mAmp)), ), ) diff --git a/edg/parts/power/motor/MotorDriver_Drv8870.py b/edg/parts/power/motor/MotorDriver_Drv8870.py index 11d106f64..16609b331 100644 --- a/edg/parts/power/motor/MotorDriver_Drv8870.py +++ b/edg/parts/power/motor/MotorDriver_Drv8870.py @@ -38,7 +38,7 @@ def __init__(self) -> None: def contents(self) -> None: self.assign( self.isen.current_draw, - (0, self.out1.link().current_drawn.abs().upper().max(self.out2.link().current_drawn.abs().upper())), + (0, self.out1.link().current_draw.abs().upper().max(self.out2.link().current_draw.abs().upper())), ) self.assign(self.vm.current_draw, (10, 10000) * uAmp + self.isen.current_draw) # from sleep to max operating diff --git a/edg/parts/power/motor/MotorDriver_L293dd.py b/edg/parts/power/motor/MotorDriver_L293dd.py index 6dd9b7b3d..6441ef655 100644 --- a/edg/parts/power/motor/MotorDriver_L293dd.py +++ b/edg/parts/power/motor/MotorDriver_L293dd.py @@ -39,11 +39,11 @@ def __init__(self) -> None: + ( 0, # calculate possible motor current, assuming A1/2 and B1/2 are coupled (and not independent) self.out1.is_connected() - .then_else(self.out1.link().current_drawn.abs().upper(), 0 * mAmp) - .max(self.out2.is_connected().then_else(self.out2.link().current_drawn.abs().upper(), 0 * mAmp)) + .then_else(self.out1.link().current_draw.abs().upper(), 0 * mAmp) + .max(self.out2.is_connected().then_else(self.out2.link().current_draw.abs().upper(), 0 * mAmp)) + self.out3.is_connected() - .then_else(self.out3.link().current_drawn.abs().upper(), 0 * mAmp) - .max(self.out4.is_connected().then_else(self.out4.link().current_drawn.abs().upper(), 0 * mAmp)), + .then_else(self.out3.link().current_draw.abs().upper(), 0 * mAmp) + .max(self.out4.is_connected().then_else(self.out4.link().current_draw.abs().upper(), 0 * mAmp)), ), ) diff --git a/edg/parts/power/motor/StepperDriver_A4988.py b/edg/parts/power/motor/StepperDriver_A4988.py index f52ddfed1..bb69a3da3 100644 --- a/edg/parts/power/motor/StepperDriver_A4988.py +++ b/edg/parts/power/motor/StepperDriver_A4988.py @@ -59,14 +59,14 @@ def __init__(self) -> None: self.out1b = self.Port(dout1_model) self.assign( self.vbb1.current_draw, - self.out1a.link().current_drawn.hull(self.out1b.link().current_drawn).abs().hull((0, 0)) + kVbbDraw, + self.out1a.link().current_draw.hull(self.out1b.link().current_draw).abs().hull((0, 0)) + kVbbDraw, ) dout2_model = DigitalSource.from_supply(self.gnd, self.vbb2, current_limits=(-2, 2) * Amp) self.out2a = self.Port(dout2_model) self.out2b = self.Port(dout2_model) self.assign( self.vbb2.current_draw, - self.out2a.link().current_drawn.hull(self.out2b.link().current_drawn).abs().hull((0, 0)) + kVbbDraw, + self.out2a.link().current_draw.hull(self.out2b.link().current_draw).abs().hull((0, 0)) + kVbbDraw, ) @override diff --git a/examples/test_datalogger.py b/examples/test_datalogger.py index 50b380174..e015b27b3 100644 --- a/examples/test_datalogger.py +++ b/examples/test_datalogger.py @@ -46,7 +46,7 @@ def __init__(self, charging_current: RangeLike, sense_resistance: RangeLike, vol self.pwr_out = self.Port(VoltageSource.empty(), [Output]) self.require( self.pwr.current_draw.within( - self.pwr_out.link().current_drawn + (0, self.charging_current.upper()) + (0, 0.05) + self.pwr_out.link().current_draw + (0, self.charging_current.upper()) + (0, 0.05) ) ) # TODO nonhacky bounds on opamp/sense resistor current draw self.sc_out = self.Port(VoltageSource.empty(), optional=True) diff --git a/examples/test_fcml.py b/examples/test_fcml.py index c85170fb4..be69f8e98 100644 --- a/examples/test_fcml.py +++ b/examples/test_fcml.py @@ -43,7 +43,7 @@ def __init__(self, reverse_voltage: RangeLike, current: RangeLike, voltage_drop: self.connect(self.pwr_in.net, self.diode.anode) self.connect(self.pwr_out.net, self.diode.cathode) - self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn) + self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) class MultilevelSwitchingCell(InternalSubcircuit, KiCadSchematicBlock, GeneratorBlock): @@ -134,7 +134,7 @@ def generate(self) -> None: # Q = C dv => C = I*t / dV MAX_FLYING_CAP_DV_PERCENT = 0.08 flying_cap_capacitance = ( - self.high_out.link().current_drawn.upper() + self.high_out.link().current_draw.upper() / self.frequency.lower() / (self.in_voltage.upper() * MAX_FLYING_CAP_DV_PERCENT) ) @@ -144,7 +144,7 @@ def generate(self) -> None: locals={ "fet_model": Fet.NFet( drain_voltage=self.in_voltage, - drain_current=(0, self.high_out.link().current_drawn.upper()), + drain_current=(0, self.high_out.link().current_draw.upper()), gate_voltage=self.low_boot_out.link().voltage, # TODO account for boot diode drop rds_on=self.fet_rds, ), @@ -169,7 +169,7 @@ def generate(self) -> None: conversions={ "low_in": Ground(), # TODO better conventions for Ground vs VoltageSink|Source "low_out": VoltageSource(voltage_out=self.low_in.link().voltage), - "high_in": VoltageSink(current_draw=self.high_out.link().current_drawn), + "high_in": VoltageSink(current_draw=self.high_out.link().current_draw), "high_out": VoltageSource(voltage_out=self.low_in.link().voltage), "low_boot_cap.1": VoltageSink(), "high_boot_cap.1": VoltageSink(), @@ -275,7 +275,7 @@ def generate(self) -> None: self.connect( self.switch, - self.inductor.a.adapt_to(VoltageSink(current_draw=self.pwr_out.link().current_drawn * values.dutycycle)), + self.inductor.a.adapt_to(VoltageSink(current_draw=self.pwr_out.link().current_draw * values.dutycycle)), ) self.connect( self.pwr_out, @@ -360,7 +360,7 @@ def generate(self) -> None: self.pwr_in.link().voltage, self.pwr_in.link().voltage * self.get(self.ratios), self.frequency, - self.pwr_out.link().current_drawn, + self.pwr_out.link().current_draw, Range.exact(0), input_voltage_ripple=250 * mVolt, output_voltage_ripple=25 * mVolt, # TODO plumb through to user config @@ -581,7 +581,7 @@ def refinements(self) -> Refinements: (["reg_vgate", "power_path", "inductor", "manual_frequency_rating"], Range.all()), # a bugfix for the SPI flash current draw increased the current beyond the USB port's capabilities # this hack-patch keeps the example building - (["vusb", "current_drawn"], Range(0.0311, 0.500)), + (["vusb", "current_draw"], Range(0.0311, 0.500)), ], class_refinements=[ (PassiveConnector, JstPhKVertical), # default connector series unless otherwise specified diff --git a/examples/test_iot_display.py b/examples/test_iot_display.py index 6d7e3323a..cd0ccd2d0 100644 --- a/examples/test_iot_display.py +++ b/examples/test_iot_display.py @@ -32,7 +32,7 @@ def contents(self) -> None: self.drv = self.Block( SwitchFet.PFet( drain_voltage=self.pwr.link().voltage, - drain_current=self.output.link().current_drawn, + drain_current=self.output.link().current_draw, gate_voltage=self.control.link().voltage - self.pwr.link().voltage, # TODO needs to be diff from pwr.voltage rds_on=(0, self.max_rds), @@ -45,7 +45,7 @@ def contents(self) -> None: self.connect(self.output.net, self.drv.drain) self.connect(self.control.net, self.drv.gate) - self.assign(self.pwr.current_draw, self.output.link().current_drawn) + self.assign(self.pwr.current_draw, self.output.link().current_draw) self.assign(self.output.current_limits, self.drv.actual_drain_current_rating) diff --git a/examples/test_lora.py b/examples/test_lora.py index d294bb080..36045c325 100644 --- a/examples/test_lora.py +++ b/examples/test_lora.py @@ -176,7 +176,7 @@ def refinements(self) -> Refinements: (["mcu", "programming"], "uart-auto-button"), (["usb", "conn", "current_limits"], Range(0.0, 1.1)), # fudge it a lot ( - ["pwr", "current_drawn"], + ["pwr", "current_draw"], Range(0.031392638, 0.8), ), # allow use of basic part ferrite, assume not everything run simultaneously ( diff --git a/examples/test_usb_source_measure.py b/examples/test_usb_source_measure.py index bed0f2e38..369528dd8 100644 --- a/examples/test_usb_source_measure.py +++ b/examples/test_usb_source_measure.py @@ -425,7 +425,7 @@ def contents(self) -> None: self.file_path("UsbSourceMeasure", f"{self.__class__.__name__}.kicad_sch"), conversions={ "input": AnalogSink( - current_draw=self.output.link().current_drawn, impedance=self.output.link().sink_impedance + current_draw=self.output.link().current_draw, impedance=self.output.link().sink_impedance ), "output": AnalogSource( voltage_out=self.input.link().voltage.intersect(self.model_voltage_clamp), @@ -648,7 +648,7 @@ def contents(self) -> None: self.Block(VoltageTestPoint("vc-")), ) self.vcontroln = self.connect( - self.reg_vcontroln.pwr_out.as_ground(current_draw=self.reg_vcontrol.pwr_out.link().current_drawn) + self.reg_vcontroln.pwr_out.as_ground(current_draw=self.reg_vcontrol.pwr_out.link().current_draw) ) # power path domain From 273f5f2fd9646aebec1677aee42909d5054755b0 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 23:19:38 -0700 Subject: [PATCH 16/23] wip --- edg/{utils => tools}/__init__.py | 0 edg/{utils => tools}/jlc_pcba/__init__.py | 0 edg/{utils => tools}/jlc_pcba/__main__.py | 0 edg/util/__init__.py | 32 +++++++++++++++++++++++ 4 files changed, 32 insertions(+) rename edg/{utils => tools}/__init__.py (100%) rename edg/{utils => tools}/jlc_pcba/__init__.py (100%) rename edg/{utils => tools}/jlc_pcba/__main__.py (100%) create mode 100644 edg/util/__init__.py diff --git a/edg/utils/__init__.py b/edg/tools/__init__.py similarity index 100% rename from edg/utils/__init__.py rename to edg/tools/__init__.py diff --git a/edg/utils/jlc_pcba/__init__.py b/edg/tools/jlc_pcba/__init__.py similarity index 100% rename from edg/utils/jlc_pcba/__init__.py rename to edg/tools/jlc_pcba/__init__.py diff --git a/edg/utils/jlc_pcba/__main__.py b/edg/tools/jlc_pcba/__main__.py similarity index 100% rename from edg/utils/jlc_pcba/__main__.py rename to edg/tools/jlc_pcba/__main__.py diff --git a/edg/util/__init__.py b/edg/util/__init__.py new file mode 100644 index 000000000..cdb6e0d5d --- /dev/null +++ b/edg/util/__init__.py @@ -0,0 +1,32 @@ +import warnings +from functools import wraps +from typing import Tuple, Callable, ParamSpec, TypeVar, Any + +P = ParamSpec("P") +R = TypeVar("R") + + +def deprecated_param_remap(*params: Tuple[str, str]) -> Callable[[Callable[P, R]], Callable[P, R]]: + """Decorator to remap deprecated parameter names to new names. + + Args: + *params: A list of tuples where each tuple contains the old parameter name and the new parameter name. + """ + + def decorator(func: Callable[P, R]) -> Callable[P, R]: + @wraps(func) + def wrapper(self, *args: Any, **kwargs: Any) -> R: + for old_param, new_param in params: + if old_param in kwargs: + warnings.warn( + f"{old_param} is deprecated and replaced with {new_param}", + DeprecationWarning, + stacklevel=2, + ) + assert new_param not in kwargs, f"both old {old_param} and new {new_param} parameters specified" + kwargs[new_param] = kwargs.pop(old_param) + return func(self, *args, **kwargs) + + return wrapper + + return decorator From 9b034c203c3358c9bf33643a226e5bd6fc6b49d8 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 23:21:29 -0700 Subject: [PATCH 17/23] voltage renaming for analog --- edg/electronics_interfaces/AnalogPort.py | 71 +++++++++++++----------- edg/electronics_model/PassivePort.py | 8 +-- 2 files changed, 43 insertions(+), 36 deletions(-) diff --git a/edg/electronics_interfaces/AnalogPort.py b/edg/electronics_interfaces/AnalogPort.py index dadde1072..835049a9b 100644 --- a/edg/electronics_interfaces/AnalogPort.py +++ b/edg/electronics_interfaces/AnalogPort.py @@ -8,6 +8,7 @@ from ..electronics_model import * from .GroundPort import GroundLink from .VoltagePorts import VoltageLink, VoltageSource +from ..util import deprecated_param_remap class AnalogLink(Link): @@ -22,8 +23,8 @@ def __init__(self) -> None: self.source_impedance = self.Parameter(RangeExpr(self.source.impedance)) self.sink_impedance = self.Parameter(RangeExpr()) - self.voltage = self.Parameter(RangeExpr(self.source.voltage_out)) - self.signal = self.Parameter(RangeExpr(self.source.signal_out)) + self.voltage = self.Parameter(RangeExpr(self.source.voltage)) + self.signal = self.Parameter(RangeExpr(self.source.signal)) self.current_draw = self.Parameter(RangeExpr()) self.voltage_limits = self.Parameter(RangeExpr()) @@ -93,7 +94,7 @@ def __init__(self) -> None: # The outer port's voltage_limits is untouched and should be defined in the port def. # TODO: it's a slightly optimization to handle them here. Should it be done? # TODO: or maybe current_limits / voltage_limits shouldn't be a port, but rather a block property? - self.inner_link = self.Port(AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr())) + self.inner_link = self.Port(AnalogSource(voltage=RangeExpr(), signal=RangeExpr())) @override def contents(self) -> None: @@ -106,8 +107,8 @@ def contents(self) -> None: self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) self.assign(self.outer_port.signal_limits, self.inner_link.link().signal_limits) - self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) - self.assign(self.inner_link.signal_out, self.outer_port.link().signal) + self.assign(self.inner_link.voltage, self.outer_port.link().voltage) + self.assign(self.inner_link.signal, self.outer_port.link().signal) class AnalogSourceBridge(PortBridge): # basic passthrough port, sources look the same inside and outside @@ -115,9 +116,7 @@ def __init__(self) -> None: super().__init__() self.outer_port = self.Port( - AnalogSource( - voltage_out=RangeExpr(), signal_out=RangeExpr(), current_limits=RangeExpr(), impedance=RangeExpr() - ) + AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), current_limits=RangeExpr(), impedance=RangeExpr()) ) # Here we ignore the voltage_limits of the inner port, instead relying on the main link to handle it @@ -137,8 +136,8 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) - self.assign(self.outer_port.signal_out, self.inner_link.link().signal) + self.assign(self.outer_port.voltage, self.inner_link.link().voltage) + self.assign(self.outer_port.signal, self.inner_link.link().signal) self.assign(self.outer_port.impedance, self.inner_link.link().source_impedance) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits @@ -217,7 +216,7 @@ def __init__(self) -> None: self.src = self.Port(AnalogSink(current_draw=RangeExpr())) # otherwise ideal self.dst = self.Port( VoltageSource( - voltage_out=(self.src.link().voltage.upper(), self.src.link().voltage.upper()), + voltage=(self.src.link().voltage.upper(), self.src.link().voltage.upper()), ) ) self.assign(self.src.current_draw, self.dst.link().current_draw) @@ -227,49 +226,59 @@ def __init__(self) -> None: class AnalogSource(HasPassivePort, AnalogBase): bridge_type = AnalogSourceBridge + @deprecated_param_remap(("signal_out_bound", "signal_bound"), ("signal_out_abs", "signal_abs")) @staticmethod def from_supply( neg: Port[GroundLink], pos: Port[VoltageLink], *, - signal_out_bound: Optional[Tuple[FloatLike, FloatLike]] = None, - signal_out_abs: Optional[RangeLike] = None, + signal_bound: Optional[Tuple[FloatLike, FloatLike]] = None, + signal_abs: Optional[RangeLike] = None, current_limits: RangeLike = RangeExpr.ALL, impedance: RangeLike = RangeExpr.ZERO, ) -> "AnalogSource": supply_range = VoltageLink._supply_voltage_range(neg, pos) - if signal_out_bound is not None: - assert signal_out_abs is None + if signal_bound is not None: + assert signal_abs is None # signal limit bounds specified as (lower bound added to limit, upper bound added to limit) # typically (positive, negative) - signal_out: RangeLike = ( - supply_range.lower() + signal_out_bound[0], - supply_range.upper() + signal_out_bound[1], + signal: RangeLike = ( + supply_range.lower() + signal_bound[0], + supply_range.upper() + signal_bound[1], ) - elif signal_out_abs is not None: - assert signal_out_bound is None - signal_out = signal_out_abs + elif signal_abs is not None: + assert signal_bound is None + signal = signal_abs else: # generic default - signal_out = supply_range + signal = supply_range - return AnalogSource( - voltage_out=supply_range, signal_out=signal_out, current_limits=current_limits, impedance=impedance - ) + return AnalogSource(voltage=supply_range, signal=signal, current_limits=current_limits, impedance=impedance) + @deprecated_param_remap(("voltage_out", "voltage"), ("signal_out", "signal")) def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, - signal_out: RangeLike = RangeExpr.EMPTY, + voltage: RangeLike = RangeExpr.ZERO, + signal: RangeLike = RangeExpr.EMPTY, current_limits: RangeLike = RangeExpr.ALL, impedance: RangeLike = RangeExpr.ZERO, ) -> None: - """voltage_out is the total voltage range the device can output (typically limited by power rails) - regardless of controls and including transients, while signal_out is the intended operating range""" + """voltage is the total voltage range the device can output (typically limited by power rails) + regardless of controls and including transients, while signal is the intended operating range""" super().__init__() self.net = self.Port(Passive()) - self.voltage_out = self.Parameter(RangeExpr(voltage_out)) - self.signal_out = self.Parameter(RangeExpr(signal_out)) + self.voltage = self.Parameter(RangeExpr(voltage)) + self.signal = self.Parameter(RangeExpr(signal)) self.current_limits = self.Parameter(RangeExpr(current_limits)) self.impedance = self.Parameter(RangeExpr(impedance)) + + @property + @deprecated(f"use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage + + @property + @deprecated(f"use signal") + def signal_out(self) -> RangeExpr: + return self.signal diff --git a/edg/electronics_model/PassivePort.py b/edg/electronics_model/PassivePort.py index 20e21417f..18a69b498 100644 --- a/edg/electronics_model/PassivePort.py +++ b/edg/electronics_model/PassivePort.py @@ -180,8 +180,8 @@ class PassiveAdapterAnalogSource(KicadImportablePortAdapter["AnalogSource"]): # TODO we can't use **kwargs b/c the init hook needs an initializer list def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, - signal_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, + signal: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, impedance: RangeLike = RangeExpr.ZERO, ): @@ -190,9 +190,7 @@ def __init__( super().__init__() self.src = self.Port(Passive()) self.dst = self.Port( - AnalogSource( - voltage_out=voltage_out, signal_out=signal_out, current_limits=current_limits, impedance=impedance - ) + AnalogSource(voltage=voltage, signal=signal, current_limits=current_limits, impedance=impedance) ) self.connect(self.src, self.dst.net) From cc8e53d52da1839302e8caedb9be307e6683b1e3 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 23:41:13 -0700 Subject: [PATCH 18/23] wip out cleanup --- edg/abstract_parts/AnalogSwitch.py | 4 +- edg/abstract_parts/Capacitor.py | 4 +- edg/abstract_parts/Resistor.py | 2 +- edg/abstract_parts/SolidStateRelay.py | 2 +- edg/abstract_parts/ZenerDiode.py | 2 +- edg/circuits/OpampCircuits.py | 4 +- edg/circuits/OpampCurrentSensor.py | 2 +- edg/circuits/PassiveFilters.py | 8 +-- edg/circuits/ResistiveDivider.py | 4 +- edg/circuits/ResistiveSensor.py | 4 +- edg/circuits/VoltageClamping.py | 2 +- edg/electronics_interfaces/DigitalPorts.py | 37 ++++++++----- edg/electronics_interfaces/DummyDevices.py | 12 +++-- edg/electronics_interfaces/GroundPort.py | 2 +- edg/electronics_interfaces/MergedBlocks.py | 4 +- edg/electronics_interfaces/VoltagePorts.py | 52 ++++++++++++------- edg/electronics_model/PassivePort.py | 12 ++--- edg/parts/analog/CurrentSense_Ad8418.py | 2 +- edg/parts/analog/dac/Mcp47f.py | 4 +- edg/parts/analog/dac/Mcp4901.py | 2 +- edg/parts/analog/opamp/Ina826.py | 6 +-- edg/parts/analog/opamp/Lmv321.py | 2 +- edg/parts/analog/opamp/Mcp6001.py | 2 +- edg/parts/analog/opamp/Opax171.py | 2 +- edg/parts/analog/opamp/Opax189.py | 2 +- edg/parts/analog/opamp/Opax197.py | 2 +- edg/parts/analog/opamp/Opax333.py | 2 +- edg/parts/analog/opamp/Tlv9061.py | 2 +- edg/parts/analog/opamp/Tlv915x.py | 2 +- .../human_interface/SpeakerDriver_Analog.py | 2 +- edg/parts/microcontroller/Lpc1549.py | 2 +- edg/parts/microcontroller/Stm32f303.py | 2 +- edg/parts/microcontroller/Stm32g431.py | 2 +- edg/parts/microcontroller/Stm32l432.py | 2 +- edg/parts/sensor/Mag_A1304.py | 2 +- examples/test_iot_iron.py | 2 +- examples/test_multimeter.py | 6 +-- examples/test_robotcrawler.py | 2 +- examples/test_robotdriver.py | 4 +- examples/test_usb_source_measure.py | 4 +- 40 files changed, 122 insertions(+), 95 deletions(-) diff --git a/edg/abstract_parts/AnalogSwitch.py b/edg/abstract_parts/AnalogSwitch.py index 975695fbd..edefd50fb 100644 --- a/edg/abstract_parts/AnalogSwitch.py +++ b/edg/abstract_parts/AnalogSwitch.py @@ -131,7 +131,7 @@ def __init__(self) -> None: self.out = self.Port( AnalogSource( voltage_out=self.inputs.hull(lambda x: x.link().voltage), - signal_out=self.inputs.hull(lambda x: x.link().signal), + signal=self.inputs.hull(lambda x: x.link().signal), current_limits=self.device.analog_current_limits, # this device only, current draw propagated impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance), ) @@ -202,7 +202,7 @@ def generate(self) -> None: output = self.outputs.append_elt( AnalogSource( voltage_out=self.input.link().voltage, - signal_out=self.input.link().signal, + signal=self.input.link().signal, current_limits=self.device.analog_current_limits, # this device only, voltages propagated impedance=self.input.link().source_impedance + self.device.analog_on_resistance, ), diff --git a/edg/abstract_parts/Capacitor.py b/edg/abstract_parts/Capacitor.py index 57e68cf16..dd87e997f 100644 --- a/edg/abstract_parts/Capacitor.py +++ b/edg/abstract_parts/Capacitor.py @@ -450,7 +450,7 @@ def __init__(self, capacitance: RangeLike, output_bias: RangeLike, *, exact_capa self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input]) self.output = self.Port( - AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr(), impedance=self.input.link().source_impedance), + AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=self.input.link().source_impedance), [Output], ) @@ -477,7 +477,7 @@ def contents(self) -> None: ) signal_halfspan = (self.input.link().signal.upper() - self.input.link().signal.lower()) / 2 self.assign( - self.output.signal_out, + self.output.signal, (self.output_bias.lower() - signal_halfspan, self.output_bias.upper() + signal_halfspan), ) diff --git a/edg/abstract_parts/Resistor.py b/edg/abstract_parts/Resistor.py index b50f50cc3..6610a8260 100644 --- a/edg/abstract_parts/Resistor.py +++ b/edg/abstract_parts/Resistor.py @@ -425,7 +425,7 @@ def __init__(self, resistance: RangeLike) -> None: self.output = self.Port( AnalogSource( voltage_out=self.input.link().voltage, - signal_out=self.input.link().signal, + signal=self.input.link().signal, impedance=self.input.link().source_impedance + self.res.actual_resistance, ), [Output], diff --git a/edg/abstract_parts/SolidStateRelay.py b/edg/abstract_parts/SolidStateRelay.py index 94265963e..6a9826fb4 100644 --- a/edg/abstract_parts/SolidStateRelay.py +++ b/edg/abstract_parts/SolidStateRelay.py @@ -102,7 +102,7 @@ def __init__(self) -> None: self.aout = self.Port( AnalogSource( voltage_out=self.ain.link().voltage, - signal_out=self.ain.link().signal, + signal=self.ain.link().signal, current_limits=self.ic.load_current_limit, impedance=self.ain.link().source_impedance + self.ic.load_resistance, ) diff --git a/edg/abstract_parts/ZenerDiode.py b/edg/abstract_parts/ZenerDiode.py index fda9ce145..f089b27fa 100644 --- a/edg/abstract_parts/ZenerDiode.py +++ b/edg/abstract_parts/ZenerDiode.py @@ -103,7 +103,7 @@ def __init__(self, voltage: RangeLike): voltage_out=self.signal_in.link().voltage.intersect( self.gnd.link().voltage + (0, self.diode.actual_zener_voltage.upper()) ), - signal_out=self.signal_in.link().signal, + signal=self.signal_in.link().signal, ), [Output], ) diff --git a/edg/circuits/OpampCircuits.py b/edg/circuits/OpampCircuits.py index 1ebef8631..49b2f435b 100644 --- a/edg/circuits/OpampCircuits.py +++ b/edg/circuits/OpampCircuits.py @@ -162,7 +162,7 @@ def generate(self) -> None: input_signal_range = self.amp.out.voltage_out.intersect(self.input.link().signal - reference_range) output_range = input_signal_range * self.actual_amplification + reference_range # TODO tolerances can cause the range to be much larger than actual, so bound it to avoid false-positives - self.forced = self.Block(ForcedAnalogSignal(self.amp.out.signal_out.intersect(output_range))) + self.forced = self.Block(ForcedAnalogSignal(self.amp.out.signal.intersect(output_range))) self.import_kicad( self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), @@ -313,7 +313,7 @@ def generate(self) -> None: input_diff_range = self.input_positive.link().signal - self.input_negative.link().signal output_diff_range = input_diff_range * self.actual_ratio + output_neg_signal # TODO tolerances can cause the range to be much larger than actual, so bound it to avoid false-positives - self.forced = self.Block(ForcedAnalogSignal(self.amp.out.signal_out.intersect(output_diff_range))) + self.forced = self.Block(ForcedAnalogSignal(self.amp.out.signal.intersect(output_diff_range))) self.import_kicad( self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), diff --git a/edg/circuits/OpampCurrentSensor.py b/edg/circuits/OpampCurrentSensor.py index bf6445904..69e2629ce 100644 --- a/edg/circuits/OpampCurrentSensor.py +++ b/edg/circuits/OpampCurrentSensor.py @@ -36,7 +36,7 @@ def contents(self) -> None: output_swing = self.pwr_out.link().current_draw * self.sense.actual_resistance * self.amp.actual_ratio self.force_signal = self.Block(ForcedAnalogSignal(output_swing + self.ref.link().signal)) self.connect(self.amp.output, self.force_signal.signal_in) - self.connect(self.force_signal.signal_out, self.out) + self.connect(self.force_signal.signal, self.out) @override def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]: diff --git a/edg/circuits/PassiveFilters.py b/edg/circuits/PassiveFilters.py index 65bf654dc..bdfa70f7b 100644 --- a/edg/circuits/PassiveFilters.py +++ b/edg/circuits/PassiveFilters.py @@ -78,7 +78,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): super().__init__() self.input = self.Port(AnalogSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( - AnalogSource(voltage_out=self.input.link().voltage, signal_out=self.input.link().signal), [Output] + AnalogSource(voltage_out=self.input.link().voltage, signal=self.input.link().signal), [Output] ) self.assign(self.input.current_draw, self.output.link().current_draw) @@ -157,7 +157,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.output = self.Port( AnalogSource( voltage_out=self.input.link().voltage, - signal_out=self.input.link().voltage, + signal=self.input.link().voltage, impedance=impedance, # TODO use selected resistance from RC filter ), [Output], @@ -186,14 +186,14 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.outn = self.Port( AnalogSource( voltage_out=self.inn.link().voltage, - signal_out=self.inn.link().signal, + signal=self.inn.link().signal, impedance=RangeExpr(), ) ) self.outp = self.Port( AnalogSource( voltage_out=self.inp.link().voltage, - signal_out=self.inp.link().signal, + signal=self.inp.link().signal, impedance=RangeExpr(), ) ) diff --git a/edg/circuits/ResistiveDivider.py b/edg/circuits/ResistiveDivider.py index 1956061ce..5f6fd36f4 100644 --- a/edg/circuits/ResistiveDivider.py +++ b/edg/circuits/ResistiveDivider.py @@ -174,7 +174,7 @@ def __init__(self, impedance: RangeLike) -> None: self.output = self.Port( AnalogSource( voltage_out=output_voltage, - signal_out=output_voltage, + signal=output_voltage, impedance=self.div.actual_impedance, ), [Output], @@ -272,7 +272,7 @@ def __init__(self, ratio: RangeLike, impedance: RangeLike) -> None: self.input.link().voltage, self.gnd.link().voltage, self.div.actual_ratio ) self.output = self.Port( - AnalogSource(voltage_out=output_voltage, signal_out=output_voltage, impedance=self.div.actual_impedance), + AnalogSource(voltage_out=output_voltage, signal=output_voltage, impedance=self.div.actual_impedance), [Output], ) self.assign(self.input.current_draw, self.output.link().current_draw) diff --git a/edg/circuits/ResistiveSensor.py b/edg/circuits/ResistiveSensor.py index 30ab909ee..cf5dfe086 100644 --- a/edg/circuits/ResistiveSensor.py +++ b/edg/circuits/ResistiveSensor.py @@ -17,7 +17,7 @@ def __init__(self, resistance_range: RangeLike, fixed_resistance: RangeLike) -> self.input = self.Port(VoltageSink(current_draw=RangeExpr()), [Power]) self.output = self.Port( - AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr(), impedance=RangeExpr()), [Output] + AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr()), [Output] ) self.gnd = self.Port(Ground(), [Common]) @@ -36,7 +36,7 @@ def contents(self) -> None: self.input.link().voltage, self.gnd.link().voltage, self.actual_ratio ) self.assign(self.output.voltage_out, output_voltage) - self.assign(self.output.signal_out, output_voltage) + self.assign(self.output.signal, output_voltage) self.assign(self.output.impedance, self.actual_impedance) self.connect(self.output.net, self.top.b, self.bot.pins.request("1")) self.connect(self.gnd.net, self.bot.pins.request("2")) diff --git a/edg/circuits/VoltageClamping.py b/edg/circuits/VoltageClamping.py index 2615d8c80..e73b6bead 100644 --- a/edg/circuits/VoltageClamping.py +++ b/edg/circuits/VoltageClamping.py @@ -33,7 +33,7 @@ def __init__( self.signal_out = self.Port( AnalogSource( voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target), - signal_out=self.signal_in.link().signal, + signal=self.signal_in.link().signal, impedance=RangeExpr(), ), [Output], diff --git a/edg/electronics_interfaces/DigitalPorts.py b/edg/electronics_interfaces/DigitalPorts.py index ccfbcec64..7de8956bc 100644 --- a/edg/electronics_interfaces/DigitalPorts.py +++ b/edg/electronics_interfaces/DigitalPorts.py @@ -8,6 +8,7 @@ from ..electronics_model import * from .GroundPort import GroundLink from .VoltagePorts import VoltageLink, VoltageSource +from ..util import deprecated_param_remap class DigitalLink(Link): @@ -78,9 +79,9 @@ def contents(self) -> None: ) # TODO clean this up, massively, like, this needs new constructs to simplify this pattern - voltage_hull = self.bidirs.hull(lambda x: x.voltage_out) + voltage_hull = self.bidirs.hull(lambda x: x.voltage) voltage_hull = self.sources.any_connected().then_else( - voltage_hull.hull(self.sources.hull(lambda x: x.voltage_out)), voltage_hull + voltage_hull.hull(self.sources.hull(lambda x: x.voltage)), voltage_hull ) self.assign(self.voltage, voltage_hull) @@ -200,7 +201,7 @@ def contents(self) -> None: self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.input_thresholds, self.inner_link.link().input_thresholds) - self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) + self.assign(self.inner_link.voltage, self.outer_port.link().voltage) self.assign(self.inner_link.output_thresholds, self.outer_port.link().output_thresholds) @@ -314,7 +315,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) + self.assign(self.outer_port.voltage, self.inner_link.link().voltage) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits ) # TODO subtract internal current draw @@ -365,7 +366,7 @@ def from_bidir(model: DigitalBidir) -> DigitalSource: model_is_empty = not model._get_initializers([]) if not model_is_empty: # DigitalSource has additional high_driver and low_driver fields return DigitalSource( - model.voltage_out, + model.voltage, model.current_limits, output_thresholds=model.output_thresholds, pullup_capable=model.pullup_capable, @@ -374,9 +375,10 @@ def from_bidir(model: DigitalBidir) -> DigitalSource: else: return DigitalSource.empty() + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, *, output_thresholds: RangeLike = RangeExpr.ALL, @@ -390,7 +392,7 @@ def __init__( self.net = self.Port(Passive()) - self.voltage_out: RangeExpr = self.Parameter(RangeExpr(voltage_out)) + self.voltage: RangeExpr = self.Parameter(RangeExpr(voltage)) self.current_limits: RangeExpr = self.Parameter(RangeExpr(current_limits)) self.output_thresholds: RangeExpr = self.Parameter(RangeExpr(output_thresholds)) @@ -405,7 +407,7 @@ def __init__( def low_from_supply(neg: Port[GroundLink], *, current_limits: RangeLike = RangeExpr.ALL) -> DigitalSource: """Sink-only digital source, eg open-drain output""" return DigitalSource( - voltage_out=neg.link().voltage, + voltage=neg.link().voltage, current_limits=current_limits, output_thresholds=(neg.link().voltage.upper(), float("inf")), high_driver=False, @@ -452,6 +454,11 @@ def pullup_from_supply(pos: Port[VoltageLink]) -> DigitalSource: def as_voltage_source(self) -> VoltageSource: return self._convert(DigitalSourceAdapterVoltageSource()) + @property + @deprecated(f"use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage + class DigitalBidirBridge(PortBridge): """A bridge for DigitalBidir ports. @@ -490,7 +497,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) + self.assign(self.outer_port.voltage, self.inner_link.link().voltage) self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) self.assign( @@ -577,7 +584,7 @@ def from_supply( return DigitalBidir( # TODO get rid of to_expr_type w/ dedicated Range conversion voltage_limits=voltage_limit, current_draw=current_draw, - voltage_out=supply_range, + voltage=supply_range, current_limits=current_limits, input_thresholds=input_threshold, output_thresholds=output_threshold, @@ -585,12 +592,13 @@ def from_supply( pulldown_capable=pulldown_capable, ) + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, *, voltage_limits: RangeLike = RangeExpr.ALL, current_draw: RangeLike = RangeExpr.ZERO, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, input_thresholds: RangeLike = RangeExpr.EMPTY, output_thresholds: RangeLike = RangeExpr.ALL, @@ -604,7 +612,7 @@ def __init__( self.voltage_limits: RangeExpr = self.Parameter(RangeExpr(voltage_limits)) self.current_draw: RangeExpr = self.Parameter(RangeExpr(current_draw)) - self.voltage_out: RangeExpr = self.Parameter(RangeExpr(voltage_out)) + self.voltage: RangeExpr = self.Parameter(RangeExpr(voltage)) self.current_limits: RangeExpr = self.Parameter(RangeExpr(current_limits)) self.input_thresholds: RangeExpr = self.Parameter(RangeExpr(input_thresholds)) self.output_thresholds: RangeExpr = self.Parameter(RangeExpr(output_thresholds)) @@ -616,6 +624,11 @@ def __init__( def as_voltage_source(self) -> VoltageSource: return self._convert(DigitalSourceAdapterVoltageSource()) + @property + @deprecated(f"use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage + class DigitalSingleSourceFake: @staticmethod diff --git a/edg/electronics_interfaces/DummyDevices.py b/edg/electronics_interfaces/DummyDevices.py index 6dbb3cf7e..b4d91551f 100644 --- a/edg/electronics_interfaces/DummyDevices.py +++ b/edg/electronics_interfaces/DummyDevices.py @@ -5,6 +5,7 @@ from .VoltagePorts import VoltageSink, VoltageSource from .DigitalPorts import DigitalSink, DigitalSource, DigitalLink from .AnalogPort import AnalogSink, AnalogSource, AnalogLink +from ..util import deprecated_param_remap DummyLinkType = TypeVar("DummyLinkType", bound=Link) @@ -41,17 +42,18 @@ def __init__(self, voltage_limit: RangeLike = RangeExpr.ALL, current_draw: Range class DummyAnalogSource(BaseDummyBlock[AnalogLink]): + @deprecated_param_remap(("voltage_out", "voltage"), ("signal_out", "signal")) def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, - signal_out: RangeLike = RangeExpr.EMPTY, + voltage: RangeLike = RangeExpr.ZERO, + signal: RangeLike = RangeExpr.EMPTY, current_limits: RangeLike = RangeExpr.ALL, impedance: RangeLike = RangeExpr.ZERO, ) -> None: super().__init__() self.io = self.Port( AnalogSource( - voltage_out=voltage_out, signal_out=signal_out, current_limits=current_limits, impedance=impedance + voltage=voltage, signal=signal, current_limits=current_limits, impedance=impedance ), [InOut], ) @@ -134,8 +136,8 @@ def __init__(self, forced_signal: RangeLike = RangeExpr()) -> None: self.signal_in = self.Port(AnalogSink(current_draw=RangeExpr()), [Input]) self.signal_out = self.Port( AnalogSource( - voltage_out=self.signal_in.link().voltage, - signal_out=forced_signal, + voltage=self.signal_in.link().voltage, + signal=forced_signal, current_limits=self.signal_in.link().current_limits, ), [Output], diff --git a/edg/electronics_interfaces/GroundPort.py b/edg/electronics_interfaces/GroundPort.py index 6d50449a0..f5f603a01 100644 --- a/edg/electronics_interfaces/GroundPort.py +++ b/edg/electronics_interfaces/GroundPort.py @@ -97,7 +97,7 @@ def __init__(self) -> None: self.dst = self.Port( AnalogSource( voltage_out=self.src.link().voltage, - signal_out=self.src.link().voltage, + signal=self.src.link().voltage, ) ) self.connect(self.dst.net, self.src.net) diff --git a/edg/electronics_interfaces/MergedBlocks.py b/edg/electronics_interfaces/MergedBlocks.py index 8e2b1e093..b8a18d64e 100644 --- a/edg/electronics_interfaces/MergedBlocks.py +++ b/edg/electronics_interfaces/MergedBlocks.py @@ -77,7 +77,7 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]: def __init__(self) -> None: super().__init__() - self.output = self.Port(AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr(), impedance=RangeExpr())) + self.output = self.Port(AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr())) self.inputs = self.Port(Vector(AnalogSink.empty())) self.generator_param(self.inputs.requested()) @@ -93,7 +93,7 @@ def generate(self) -> None: self.connect(self.output.net, elt_port.net) self.assign(self.output.voltage_out, self.inputs.hull(lambda x: x.link().voltage)) - self.assign(self.output.signal_out, self.inputs.hull(lambda x: x.link().signal)) + self.assign(self.output.signal, self.inputs.hull(lambda x: x.link().signal)) self.assign( self.output.impedance, # covering cases of any or all sources driving self.inputs.hull(lambda x: x.link().source_impedance).hull( diff --git a/edg/electronics_interfaces/VoltagePorts.py b/edg/electronics_interfaces/VoltagePorts.py index 21a7528de..4131db299 100644 --- a/edg/electronics_interfaces/VoltagePorts.py +++ b/edg/electronics_interfaces/VoltagePorts.py @@ -7,6 +7,7 @@ from ..electronics_model import * from .GroundPort import GroundLink, GroundReference +from ..util import deprecated_param_remap if TYPE_CHECKING: from .DigitalPorts import DigitalSource @@ -18,7 +19,7 @@ class VoltageLink(Link): def _voltage_range(cls, port: Port[VoltageLink]) -> RangeExpr: """Returns the voltage for a Voltage port, either sink or source""" if isinstance(port, VoltageSource): - return port.voltage_out + return port.voltage elif isinstance(port, VoltageSink): return port.link().voltage else: @@ -62,7 +63,7 @@ def contents(self) -> None: self.net = self.connect(self.source.net, self.sinks.map_extract(lambda x: x.net), flatten=True) - self.assign(self.voltage, self.source.voltage_out) + self.assign(self.voltage, self.source.voltage) self.assign(self.voltage_limits, self.sinks.intersection(lambda x: x.voltage_limits)) self.require(self.voltage_limits.contains(self.voltage), "voltage out of limits") self.assign(self.current_limits, self.source.current_limits) @@ -70,7 +71,7 @@ def contents(self) -> None: self.require(self.current_limits.contains(self.current_draw), "current draw out of limits") has_reverse_voltage = self.reverse_voltage != RangeExpr.EMPTY - self.assign(self.reverse_voltage, self.sinks.hull(lambda x: x.reverse_voltage_out)) + self.assign(self.reverse_voltage, self.sinks.hull(lambda x: x.reverse_voltage)) self.assign(self.reverse_voltage_limits, self.source.reverse_voltage_limits) # use implications to gate the reverse voltage requirements, since not all sources will support reverse voltage self.require( @@ -78,7 +79,7 @@ def contents(self) -> None: "reverse voltage source must have reverse voltage sink", ) self.require( - (~(self.sinks.map_extract(lambda x: x.reverse_voltage_out).elts_equals(RangeExpr.EMPTY))).count() <= 1, + (~(self.sinks.map_extract(lambda x: x.reverse_voltage).elts_equals(RangeExpr.EMPTY))).count() <= 1, "multiple reverse voltage sources not allowed", ) @@ -121,7 +122,7 @@ def __init__(self) -> None: VoltageSink( current_draw=RangeExpr(), voltage_limits=RangeExpr(), - reverse_voltage_out=RangeExpr(), + reverse_voltage=RangeExpr(), reverse_current_limits=RangeExpr(), ) ) @@ -133,7 +134,7 @@ def __init__(self) -> None: # However, reverse_voltage_limit is assigned explicitly since it determines reverse sink support self.inner_link = self.Port( VoltageSource( - voltage_out=RangeExpr(), + voltage=RangeExpr(), reverse_voltage_limits=RangeExpr(), reverse_current_draw=RangeExpr(), ) @@ -147,10 +148,10 @@ def contents(self) -> None: self.assign(self.outer_port.current_draw, self.inner_link.link().current_draw) self.assign(self.outer_port.voltage_limits, self.inner_link.link().voltage_limits) - self.assign(self.outer_port.reverse_voltage_out, self.inner_link.link().reverse_voltage) + self.assign(self.outer_port.reverse_voltage, self.inner_link.link().reverse_voltage) self.assign(self.outer_port.reverse_current_limits, self.inner_link.link().reverse_current_limits) - self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) + self.assign(self.inner_link.voltage, self.outer_port.link().voltage) self.assign(self.inner_link.reverse_voltage_limits, self.outer_port.link().reverse_voltage_limits) self.assign(self.inner_link.reverse_current_draw, self.outer_port.link().reverse_current_draw) @@ -161,7 +162,7 @@ def __init__(self) -> None: self.outer_port = self.Port( VoltageSource( - voltage_out=RangeExpr(), + voltage=RangeExpr(), current_limits=RangeExpr(), reverse_voltage_limits=RangeExpr(), reverse_current_draw=RangeExpr(), @@ -175,7 +176,7 @@ def __init__(self) -> None: self.inner_link = self.Port( VoltageSink( current_draw=RangeExpr(), - reverse_voltage_out=RangeExpr(), + reverse_voltage=RangeExpr(), reverse_current_limits=RangeExpr.ALL, ) ) @@ -186,7 +187,7 @@ def contents(self) -> None: self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.outer_port.voltage_out, self.inner_link.link().voltage) + self.assign(self.outer_port.voltage, self.inner_link.link().voltage) self.assign( self.outer_port.current_limits, self.inner_link.link().current_limits ) # TODO adjust for inner current draw @@ -194,7 +195,7 @@ def contents(self) -> None: self.assign(self.outer_port.reverse_current_draw, self.inner_link.link().reverse_current_draw) self.assign(self.inner_link.current_draw, self.outer_port.link().current_draw) - self.assign(self.inner_link.reverse_voltage_out, self.outer_port.link().reverse_voltage) + self.assign(self.inner_link.reverse_voltage, self.outer_port.link().reverse_voltage) class VoltageBase(Port[VoltageLink]): @@ -229,7 +230,7 @@ def __init__( self, voltage_limits: RangeLike = RangeExpr.ALL, current_draw: RangeLike = RangeExpr.ZERO, - reverse_voltage_out: RangeLike = RangeExpr.EMPTY, + reverse_voltage: RangeLike = RangeExpr.EMPTY, reverse_current_limits: RangeLike = RangeExpr.EMPTY, ) -> None: super().__init__() @@ -239,9 +240,14 @@ def __init__( self.voltage_limits: RangeExpr = self.Parameter(RangeExpr(voltage_limits)) self.current_draw: RangeExpr = self.Parameter(RangeExpr(current_draw)) - self.reverse_voltage_out: RangeExpr = self.Parameter(RangeExpr(reverse_voltage_out)) + self.reverse_voltage: RangeExpr = self.Parameter(RangeExpr(reverse_voltage)) self.reverse_current_limits: RangeExpr = self.Parameter(RangeExpr(reverse_current_limits)) + @property + @deprecated(f"use reverse_voltage") + def reverse_voltage_out(self) -> RangeExpr: + return self.reverse_voltage + class VoltageSinkAdapterGroundReference(PortAdapter["GroundReference"]): def __init__(self, current_draw: RangeLike): @@ -249,7 +255,7 @@ def __init__(self, current_draw: RangeLike): from .GroundPort import GroundReference self.src = self.Port(VoltageSink(current_draw=current_draw)) - self.dst = self.Port(GroundReference(voltage_out=self.src.link().voltage)) + self.dst = self.Port(GroundReference(voltage=self.src.link().voltage)) self.connect(self.src.net, self.dst.net) @@ -261,7 +267,7 @@ def __init__(self) -> None: self.src = self.Port(VoltageSink(current_draw=RangeExpr())) self.dst = self.Port( DigitalSource( - voltage_out=self.src.link().voltage, + voltage=self.src.link().voltage, output_thresholds=(FloatExpr._to_expr_type(-float("inf")), self.src.link().voltage.upper()), ) ) @@ -278,8 +284,8 @@ def __init__(self) -> None: self.src = self.Port(VoltageSink(current_draw=RangeExpr())) self.dst = self.Port( AnalogSource( - voltage_out=self.src.link().voltage, - signal_out=self.src.link().voltage, + voltage=self.src.link().voltage, + signal=self.src.link().voltage, impedance=(0, 0) * Ohm, # TODO not actually true, but pretty darn low? ) ) @@ -290,9 +296,10 @@ def __init__(self) -> None: class VoltageSource(HasPassivePort, VoltageBase): bridge_type = VoltageSourceBridge + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, reverse_voltage_limits: RangeLike = RangeExpr.EMPTY, reverse_current_draw: RangeLike = RangeExpr.EMPTY, @@ -301,11 +308,16 @@ def __init__( self.net = self.Port(Passive()) - self.voltage_out: RangeExpr = self.Parameter(RangeExpr(voltage_out)) + self.voltage: RangeExpr = self.Parameter(RangeExpr(voltage)) self.current_limits: RangeExpr = self.Parameter(RangeExpr(current_limits)) self.reverse_voltage_limits: RangeExpr = self.Parameter(RangeExpr(reverse_voltage_limits)) self.reverse_current_draw: RangeExpr = self.Parameter(RangeExpr(reverse_current_draw)) + @property + @deprecated(f"use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage + Power = PortTag(VoltageSink) # General positive voltage port, should only be mutually exclusive with the below diff --git a/edg/electronics_model/PassivePort.py b/edg/electronics_model/PassivePort.py index 18a69b498..ea9a179f7 100644 --- a/edg/electronics_model/PassivePort.py +++ b/edg/electronics_model/PassivePort.py @@ -37,7 +37,7 @@ class PassiveAdapterVoltageSource(PortAdapter["VoltageSource"]): # TODO we can't use **kwargs b/c init_in_parent needs the initializer list def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, reverse_voltage_limits: RangeLike = RangeExpr.EMPTY, reverse_current_draw: RangeLike = RangeExpr.EMPTY, @@ -48,7 +48,7 @@ def __init__( self.src = self.Port(Passive()) self.dst = self.Port( VoltageSource( - voltage_out=voltage_out, + voltage=voltage, current_limits=current_limits, reverse_voltage_limits=reverse_voltage_limits, reverse_current_draw=reverse_current_draw, @@ -63,7 +63,7 @@ def __init__( self, voltage_limits: RangeLike = RangeExpr.ALL, current_draw: RangeLike = RangeExpr.ZERO, - reverse_voltage_out: RangeLike = RangeExpr.EMPTY, + reverse_voltage: RangeLike = RangeExpr.EMPTY, reverse_current_limits: RangeLike = RangeExpr.EMPTY, ): from ..electronics_interfaces.VoltagePorts import VoltageSink @@ -74,7 +74,7 @@ def __init__( VoltageSink( voltage_limits=voltage_limits, current_draw=current_draw, - reverse_voltage_out=reverse_voltage_out, + reverse_voltage_out=reverse_voltage, reverse_current_limits=reverse_current_limits, ) ) @@ -85,7 +85,7 @@ class PassiveAdapterDigitalSource(PortAdapter["DigitalSource"]): # TODO we can't use **kwargs b/c the init hook needs an initializer list def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, output_thresholds: RangeLike = RangeExpr.ALL, pullup_capable: BoolLike = False, @@ -100,7 +100,7 @@ def __init__( self.src = self.Port(Passive()) self.dst = self.Port( DigitalSource( - voltage_out=voltage_out, + voltage=voltage, current_limits=current_limits, output_thresholds=output_thresholds, pullup_capable=pullup_capable, diff --git a/edg/parts/analog/CurrentSense_Ad8418.py b/edg/parts/analog/CurrentSense_Ad8418.py index 28f40f32d..1cbe9cfdd 100644 --- a/edg/parts/analog/CurrentSense_Ad8418.py +++ b/edg/parts/analog/CurrentSense_Ad8418.py @@ -31,7 +31,7 @@ def __init__(self, in_diff_range: RangeLike): self.out = self.Port( AnalogSource( voltage_out=(0.032, self.vs.link().voltage.upper() - 0.032), - signal_out=(self.vref1.link().signal + self.vref2.link().signal) / 2 + (self.in_diff_range * self.GAIN), + signal=(self.vref1.link().signal + self.vref2.link().signal) / 2 + (self.in_diff_range * self.GAIN), impedance=2 * Ohm(tol=0), # range not specified ) ) diff --git a/edg/parts/analog/dac/Mcp47f.py b/edg/parts/analog/dac/Mcp47f.py index 4521b7fbc..ef20be8f2 100644 --- a/edg/parts/analog/dac/Mcp47f.py +++ b/edg/parts/analog/dac/Mcp47f.py @@ -21,14 +21,14 @@ def __init__(self, addr_lsb: IntLike) -> None: out_ref0_model = AnalogSource.from_supply( self.vss, self.vref0, - signal_out_bound=(0.01 * Volt, -0.016 * Volt), # output amp min / max voltages + signal_bound=(0.01 * Volt, -0.016 * Volt), # output amp min / max voltages current_limits=(-3, 3) * mAmp, # short circuit current, typ impedance=(122, 900) * Ohm, # derived from assumed Vout=Vdd=2.7v, Isc=3-22mA ) out_ref1_model = AnalogSource.from_supply( self.vss, self.vref1, - signal_out_bound=(0.01 * Volt, -0.016 * Volt), # output amp min / max voltages + signal_bound=(0.01 * Volt, -0.016 * Volt), # output amp min / max voltages current_limits=(-3, 3) * mAmp, # short circuit current, typ impedance=(122, 900) * Ohm, # derived from assumed Vout=Vdd=2.7v, Isc=3-22mA ) diff --git a/edg/parts/analog/dac/Mcp4901.py b/edg/parts/analog/dac/Mcp4901.py index 8294b1640..9cdae43a5 100644 --- a/edg/parts/analog/dac/Mcp4901.py +++ b/edg/parts/analog/dac/Mcp4901.py @@ -20,7 +20,7 @@ def __init__(self) -> None: AnalogSource.from_supply( self.vss, self.vref, - signal_out_bound=(0.01 * Volt, -0.04 * Volt), # output swing + signal_bound=(0.01 * Volt, -0.04 * Volt), # output swing current_limits=(-15, 15) * mAmp, # short circuit current, typ impedance=(171, 273) * Ohm, # derived from assumed Vout=2Vref=4.096, Isc=24mA or 15mA ) diff --git a/edg/parts/analog/opamp/Ina826.py b/edg/parts/analog/opamp/Ina826.py index a4138e01d..168a5f13c 100644 --- a/edg/parts/analog/opamp/Ina826.py +++ b/edg/parts/analog/opamp/Ina826.py @@ -36,7 +36,7 @@ def __init__(self) -> None: AnalogSource.from_supply( self.vsn, self.vsp, - signal_out_bound=(0.1 * Volt, -0.15 * Volt), + signal_bound=(0.1 * Volt, -0.15 * Volt), current_limits=(-16, 16) * mAmp, # continuous to Vs/2 impedance=100 * Ohm(tol=0), # no tolerance bounds given on datasheet; open-loop impedance ) @@ -135,7 +135,7 @@ def generate(self) -> None: ) input_diff_range = self.input_positive.link().signal - self.input_negative.link().signal output_diff_range = input_diff_range * self.actual_ratio + output_neg_signal - self.forced = self.Block(ForcedAnalogSignal(self.ic.out.signal_out.intersect(output_diff_range))) + self.forced = self.Block(ForcedAnalogSignal(self.ic.out.signal.intersect(output_diff_range))) self.connect(self.forced.signal_in, self.ic.out) - self.connect(self.forced.signal_out, self.output) + self.connect(self.forced.signal, self.output) diff --git a/edg/parts/analog/opamp/Lmv321.py b/edg/parts/analog/opamp/Lmv321.py index 57bfbb46e..142e95b08 100644 --- a/edg/parts/analog/opamp/Lmv321.py +++ b/edg/parts/analog/opamp/Lmv321.py @@ -24,7 +24,7 @@ def __init__(self) -> None: AnalogSource.from_supply( self.vss, self.vcc, - signal_out_bound=(0.180 * Volt, -0.100 * Volt), # assuming a 10k load, Vcc=2.7v + signal_bound=(0.180 * Volt, -0.100 * Volt), # assuming a 10k load, Vcc=2.7v current_limits=(-40, 40) * mAmp, # output short circuit current ) ) diff --git a/edg/parts/analog/opamp/Mcp6001.py b/edg/parts/analog/opamp/Mcp6001.py index fad0abe87..4246bee14 100644 --- a/edg/parts/analog/opamp/Mcp6001.py +++ b/edg/parts/analog/opamp/Mcp6001.py @@ -23,7 +23,7 @@ def __init__(self) -> None: AnalogSource.from_supply( self.vss, self.vcc, - signal_out_bound=(25 * mVolt, -25 * mVolt), # maximum output swing + signal_bound=(25 * mVolt, -25 * mVolt), # maximum output swing current_limits=(-6, 6) * mAmp, # for Vdd=1.8, 23mA for Vdd=5.5 impedance=300 * Ohm(tol=0), # no tolerance bounds given on datasheet ) diff --git a/edg/parts/analog/opamp/Opax171.py b/edg/parts/analog/opamp/Opax171.py index 639fe1adf..68d1c014d 100644 --- a/edg/parts/analog/opamp/Opax171.py +++ b/edg/parts/analog/opamp/Opax171.py @@ -21,7 +21,7 @@ def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, - signal_out_bound=(0.350 * Volt, -0.350 * Volt), # output swing from rail, 10k load, over temperature + signal_bound=(0.350 * Volt, -0.350 * Volt), # output swing from rail, 10k load, over temperature current_limits=(-35, 25) * mAmp, # short circuit current impedance=150 * Ohm(tol=0), # open-loop resistance ) diff --git a/edg/parts/analog/opamp/Opax189.py b/edg/parts/analog/opamp/Opax189.py index 1affe7a3b..e4039cff6 100644 --- a/edg/parts/analog/opamp/Opax189.py +++ b/edg/parts/analog/opamp/Opax189.py @@ -21,7 +21,7 @@ def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, - signal_out_bound=(0.110 * Volt, -0.111 * Volt), # output swing from rail, assumed at 10k load + signal_bound=(0.110 * Volt, -0.111 * Volt), # output swing from rail, assumed at 10k load current_limits=(-65, 65) * mAmp, # for +/-18V supply impedance=380 * Ohm(tol=0), # open-loop impedance; no tolerance bounds specified ) diff --git a/edg/parts/analog/opamp/Opax197.py b/edg/parts/analog/opamp/Opax197.py index a4710c095..2fbd93208 100644 --- a/edg/parts/analog/opamp/Opax197.py +++ b/edg/parts/analog/opamp/Opax197.py @@ -21,7 +21,7 @@ def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, - signal_out_bound=(0.125 * Volt, -0.125 * Volt), # output swing from rail, assumed at 10k load + signal_bound=(0.125 * Volt, -0.125 * Volt), # output swing from rail, assumed at 10k load current_limits=(-65, 65) * mAmp, # for +/-18V supply impedance=375 * Ohm(tol=0), # no tolerance bounds given on datasheet; open-loop impedance ) diff --git a/edg/parts/analog/opamp/Opax333.py b/edg/parts/analog/opamp/Opax333.py index c9fa90f9d..b80290c64 100644 --- a/edg/parts/analog/opamp/Opax333.py +++ b/edg/parts/analog/opamp/Opax333.py @@ -26,7 +26,7 @@ def __init__(self) -> None: analog_out_model = AnalogSource.from_supply( self.vn, self.vp, - signal_out_bound=(70 * mVolt, -70 * mVolt), # output swing from rail, assumed at 10k load + signal_bound=(70 * mVolt, -70 * mVolt), # output swing from rail, assumed at 10k load current_limits=(-5, 5) * mAmp, # short circuit current impedance=2 * kOhm(tol=0), # open loop output impedance ) diff --git a/edg/parts/analog/opamp/Tlv9061.py b/edg/parts/analog/opamp/Tlv9061.py index 760c592ed..b5643c1eb 100644 --- a/edg/parts/analog/opamp/Tlv9061.py +++ b/edg/parts/analog/opamp/Tlv9061.py @@ -24,7 +24,7 @@ def __init__(self) -> None: AnalogSource.from_supply( self.vss, self.vcc, - signal_out_bound=(0, 0), # output voltage range V- to V+ + signal_bound=(0, 0), # output voltage range V- to V+ current_limits=(-50, 50) * mAmp, # for Vs=5V impedance=100 * Ohm(tol=0), # no tolerance bounds given on datasheet; open-loop impedance ) diff --git a/edg/parts/analog/opamp/Tlv915x.py b/edg/parts/analog/opamp/Tlv915x.py index 067e57833..977d939f1 100644 --- a/edg/parts/analog/opamp/Tlv915x.py +++ b/edg/parts/analog/opamp/Tlv915x.py @@ -26,7 +26,7 @@ def __init__(self) -> None: analog_out_model = AnalogSource.from_supply( self.vn, self.vp, - signal_out_bound=(55 * mVolt, -55 * mVolt), # output swing from rail, assumed at 10k load, Vs=16v + signal_bound=(55 * mVolt, -55 * mVolt), # output swing from rail, assumed at 10k load, Vs=16v current_limits=(-75, 75) * mAmp, # short circuit current impedance=525 * kOhm(tol=0), # open loop output impedance ) diff --git a/edg/parts/human_interface/SpeakerDriver_Analog.py b/edg/parts/human_interface/SpeakerDriver_Analog.py index 5a73b519c..b31cc8ac0 100644 --- a/edg/parts/human_interface/SpeakerDriver_Analog.py +++ b/edg/parts/human_interface/SpeakerDriver_Analog.py @@ -25,7 +25,7 @@ def __init__(self) -> None: self.vo2 = self.Port(AnalogSource()) half_vdd = (self.pwr.link().voltage - self.gnd.link().voltage) / 2 + self.gnd.link().voltage - self.byp = self.Port(AnalogSource(voltage_out=half_vdd, signal_out=half_vdd)) + self.byp = self.Port(AnalogSource(voltage_out=half_vdd, signal=half_vdd)) @override def contents(self) -> None: diff --git a/edg/parts/microcontroller/Lpc1549.py b/edg/parts/microcontroller/Lpc1549.py index 3b17ac83e..7c706b92c 100644 --- a/edg/parts/microcontroller/Lpc1549.py +++ b/edg/parts/microcontroller/Lpc1549.py @@ -123,7 +123,7 @@ def _io_pinmap(self) -> PinMapUtil: dac_model = AnalogSource.from_supply( self.gnd, self.pwr, - signal_out_bound=(0, -0.3 * Volt), + signal_bound=(0, -0.3 * Volt), current_limits=RangeExpr.ALL, # not given by spec impedance=(300, 300) * Ohm, # Table 25, "typical" rating ) diff --git a/edg/parts/microcontroller/Stm32f303.py b/edg/parts/microcontroller/Stm32f303.py index 0d9a10771..fde5e7fe9 100644 --- a/edg/parts/microcontroller/Stm32f303.py +++ b/edg/parts/microcontroller/Stm32f303.py @@ -175,7 +175,7 @@ def _io_pinmap(self) -> PinMapUtil: * kOhm(tol=0), # TODO: actually spec'd as maximum external impedance; internal impedance not given ) dac_model = AnalogSource.from_supply( - self.gnd, vdd, signal_out_bound=(0.2 * Volt, -0.2 * Volt), impedance=15 * kOhm(tol=0) # assumes buffer off + self.gnd, vdd, signal_bound=(0.2 * Volt, -0.2 * Volt), impedance=15 * kOhm(tol=0) # assumes buffer off ) uart_model = UartPort(DigitalBidir.empty()) diff --git a/edg/parts/microcontroller/Stm32g431.py b/edg/parts/microcontroller/Stm32g431.py index b6c40f229..83b7b250d 100644 --- a/edg/parts/microcontroller/Stm32g431.py +++ b/edg/parts/microcontroller/Stm32g431.py @@ -121,7 +121,7 @@ def _io_pinmap(self) -> PinMapUtil: dac_model = AnalogSource.from_supply( self.gnd, self.pwr, - signal_out_bound=(0.2 * Volt, -0.2 * Volt), # signal_out_bound only applies when output buffer on + signal_bound=(0.2 * Volt, -0.2 * Volt), # signal_bound only applies when output buffer on impedance=(9.6, 13.8) * kOhm, # assumes buffer off ) self.nrst.init_from( diff --git a/edg/parts/microcontroller/Stm32l432.py b/edg/parts/microcontroller/Stm32l432.py index a8ae437dc..06adae112 100644 --- a/edg/parts/microcontroller/Stm32l432.py +++ b/edg/parts/microcontroller/Stm32l432.py @@ -118,7 +118,7 @@ def _io_pinmap(self) -> PinMapUtil: dac_model = AnalogSource.from_supply( self.gnd, self.pwr, - signal_out_bound=(0, 0), # 0-Vref w/ DAC output buffer off + signal_bound=(0, 0), # 0-Vref w/ DAC output buffer off impedance=(9.6, 13.8) * kOhm, # DAC buffer off ) diff --git a/edg/parts/sensor/Mag_A1304.py b/edg/parts/sensor/Mag_A1304.py index 475d9c712..366bd1ffc 100644 --- a/edg/parts/sensor/Mag_A1304.py +++ b/edg/parts/sensor/Mag_A1304.py @@ -17,7 +17,7 @@ def __init__(self) -> None: ) self.vout = self.Port( AnalogSource.from_supply( - self.gnd, self.vcc, signal_out_abs=(0.38, 2.87) # output saturation limits @ Vcc=3.3v + self.gnd, self.vcc, signal_abs=(0.38, 2.87) # output saturation limits @ Vcc=3.3v ) ) diff --git a/examples/test_iot_iron.py b/examples/test_iot_iron.py index a7d8949db..f2e0e40bc 100644 --- a/examples/test_iot_iron.py +++ b/examples/test_iot_iron.py @@ -22,7 +22,7 @@ def __init__( self.thermocouple = self.Port( AnalogSource( voltage_out=self.gnd.link().voltage + (0, 14.3) * mVolt, - signal_out=self.gnd.link().voltage + (0, 14.3) * mVolt, # up to ~350 C + signal=self.gnd.link().voltage + (0, 14.3) * mVolt, # up to ~350 C ), optional=True, ) diff --git a/examples/test_multimeter.py b/examples/test_multimeter.py index 1b17d2bd6..0a44e31c4 100644 --- a/examples/test_multimeter.py +++ b/examples/test_multimeter.py @@ -88,7 +88,7 @@ def contents(self) -> None: "input_positive": AnalogSink(), "output": AnalogSource( # assumed clamped by the switch in the resistor mux voltage_out=output_voltage, - signal_out=output_voltage, + signal=output_voltage, current_limits=(-10, 10) * mAmp, impedance=1 * mOhm(tol=0), ), @@ -167,7 +167,7 @@ def contents(self) -> None: ), "range.sw": AnalogSource( voltage_out=(0, max_in_voltage), - signal_out=(0, max_in_voltage), + signal=(0, max_in_voltage), impedance=(1, 1000) * kOhm, # TODO properly model resistor mux ), "output": AnalogSink(voltage_limits=self.voltage_rating), # TODO should be analog source @@ -312,7 +312,7 @@ def contents(self) -> None: inp_port = self.inp.port.adapt_to( AnalogSource( voltage_out=VOLTAGE_RATING, - signal_out=VOLTAGE_RATING, + signal=VOLTAGE_RATING, current_limits=(0, 10) * mAmp, impedance=(0, 100) * Ohm, ) diff --git a/examples/test_robotcrawler.py b/examples/test_robotcrawler.py index 63ad17cad..f17927f56 100644 --- a/examples/test_robotcrawler.py +++ b/examples/test_robotcrawler.py @@ -22,7 +22,7 @@ def __init__(self) -> None: AnalogSource( # no specs given voltage_out=(0.9, 2.1) * Volt, # from https://www.pololu.com/blog/814/new-products-special-servos-with-position-feedback - signal_out=(0.9, 2.1) * Volt, + signal=(0.9, 2.1) * Volt, ) ) diff --git a/examples/test_robotdriver.py b/examples/test_robotdriver.py index 05f3377e7..fda67cce4 100644 --- a/examples/test_robotdriver.py +++ b/examples/test_robotdriver.py @@ -224,14 +224,14 @@ def refinements(self) -> Refinements: "tof_reset_2=12", ], ), - (["isense", "out", "signal_out"], Range(0.1, 2.45)), # trade range for resolution + (["isense", "out", "signal"], Range(0.1, 2.45)), # trade range for resolution (["isense", "sense", "res", "res", "footprint_spec"], "Resistor_SMD:R_2512_6332Metric"), (["isense", "sense", "res", "res", "require_basic_part"], False), # JLC does not have frequency specs, must be checked TODO (["reg_3v3", "power_path", "inductor", "frequency"], Range(0, 0)), (["reg_3v3", "power_path", "efficiency"], Range(1.0, 1.0)), # waive this check ( - ["mcu", "dac", "spk", "signal_out"], + ["mcu", "dac", "spk", "signal"], Range(0.65, 2.65), ), # restrict the range to the speaker driver limits, ], diff --git a/examples/test_usb_source_measure.py b/examples/test_usb_source_measure.py index 369528dd8..5a3c92540 100644 --- a/examples/test_usb_source_measure.py +++ b/examples/test_usb_source_measure.py @@ -370,7 +370,7 @@ def generate(self) -> None: "actual": AnalogSink(impedance=self.rtop.actual_resistance + self.rbot.actual_resistance), "rtop.2": AnalogSource( voltage_out=self.target.link().voltage.hull(self.actual.link().voltage), - signal_out=self.target.link().voltage.hull(self.actual.link().voltage), + signal=self.target.link().voltage.hull(self.actual.link().voltage), impedance=1 / (1 / self.rtop.actual_resistance + 1 / self.rbot.actual_resistance), ), "rbot.2": AnalogSink(), # ideal, rtop.2 contains the parameter model @@ -429,7 +429,7 @@ def contents(self) -> None: ), "output": AnalogSource( voltage_out=self.input.link().voltage.intersect(self.model_voltage_clamp), - signal_out=self.input.link().signal.intersect(self.model_signal_clamp), + signal=self.input.link().signal.intersect(self.model_signal_clamp), impedance=self.input.link().source_impedance, ), }, From d78d30d0552ca9e10035bf009c66bb42d4e6292b Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Wed, 24 Jun 2026 23:59:12 -0700 Subject: [PATCH 19/23] wip rename voltages --- edg/abstract_parts/AnalogSwitch.py | 4 +-- edg/abstract_parts/Battery.py | 2 +- edg/abstract_parts/Capacitor.py | 4 +-- edg/abstract_parts/FerriteBead.py | 2 +- edg/abstract_parts/Fuse.py | 2 +- edg/abstract_parts/Inductor.py | 2 +- .../IoControllerInterfaceMixins.py | 6 ++-- edg/abstract_parts/Jumper.py | 8 +++--- edg/abstract_parts/LinearRegulator.py | 6 ++-- edg/abstract_parts/Resistor.py | 10 +++---- edg/abstract_parts/SolidStateRelay.py | 4 +-- .../SwitchingVoltageRegulator.py | 8 +++--- edg/abstract_parts/VoltageRegulator.py | 6 ++-- edg/abstract_parts/ZenerDiode.py | 2 +- edg/abstract_parts/test_pinmappable.py | 8 ++---- edg/circuits/BoostConverterPowerPath.py | 2 +- edg/circuits/BootstrapCapacitor.py | 6 ++-- edg/circuits/BuckBoostConverterPowerPath.py | 2 +- edg/circuits/BuckConverterPowerPath.py | 2 +- edg/circuits/ControlCircuits.py | 2 +- edg/circuits/DigitalAmplifiers.py | 4 +-- edg/circuits/LevelShifter.py | 8 +++--- edg/circuits/OpampCircuits.py | 12 ++++---- edg/circuits/OpampCurrentSensor.py | 2 +- edg/circuits/PassiveFilters.py | 10 +++---- edg/circuits/PowerCircuits.py | 4 +-- edg/circuits/PowerConditioning.py | 20 ++++++------- edg/circuits/ResistiveDivider.py | 4 +-- edg/circuits/ResistiveSensor.py | 4 +-- edg/circuits/SwitchMatrix.py | 2 +- edg/circuits/UsbBitBang.py | 2 +- edg/circuits/VoltageClamping.py | 4 +-- edg/circuits/test_diodemerge.py | 6 ++-- edg/circuits/test_power_circuits.py | 4 +-- .../CircuitPackingBlock.py | 8 +++--- edg/electronics_interfaces/CrystalPort.py | 14 ++++++++-- edg/electronics_interfaces/DigitalPorts.py | 20 ++++++------- edg/electronics_interfaces/DummyDevices.py | 19 ++++++------- edg/electronics_interfaces/GroundPort.py | 28 +++++++++++-------- edg/electronics_interfaces/MergedBlocks.py | 12 ++++---- edg/electronics_interfaces/VoltageDummy.py | 8 +++--- .../test_voltage_link.py | 28 +++++++++---------- edg/electronics_model/PassivePort.py | 6 ++-- edg/parts/Jacdac.py | 6 ++-- edg/parts/analog/CurrentSense_Ad8418.py | 2 +- edg/parts/analog/adc/Mcp3561.py | 2 +- edg/parts/analog/opamp/Ina826.py | 2 +- edg/parts/connector/Connectors.py | 12 ++++---- edg/parts/connector/FanConnector.py | 2 +- edg/parts/connector/UsbPorts.py | 17 ++++++----- edg/parts/display/EInkBoostPowerPath.py | 16 ++++++----- edg/parts/display/EInk_Er_Epd027_2.py | 10 +++---- edg/parts/display/Waveshare_Epd.py | 12 ++++---- edg/parts/display/oled/Er_Oled_022.py | 2 +- edg/parts/display/oled/Er_Oled_028.py | 4 +-- edg/parts/display/oled/Er_Oled_091_3.py | 4 +-- edg/parts/display/oled/Er_Oled_096_1_1.py | 4 +-- edg/parts/display/oled/Er_Oled_096_1c.py | 4 +-- edg/parts/display/oled/test_oled_i2c_spi.py | 4 +-- .../human_interface/SpeakerDriver_Analog.py | 2 +- edg/parts/interface/CanTransceiver_Iso1050.py | 2 +- .../interface/CanTransceiver_Sn65hvd230.py | 2 +- edg/parts/interface/Rf_Pn7160.py | 6 ++-- edg/parts/interface/Rf_Sx1262.py | 6 ++-- edg/parts/interface/UsbInterface_Ft232h.py | 8 +++--- edg/parts/interface/UsbPd_Fusb302b.py | 2 +- edg/parts/interface/UsbUart_Cp2102.py | 2 +- edg/parts/microcontroller/Ch32v003.py | 2 +- edg/parts/microcontroller/Ch32v203.py | 2 +- edg/parts/microcontroller/Esp32.py | 4 +-- edg/parts/microcontroller/Esp32c3.py | 6 ++-- edg/parts/microcontroller/Esp32s3.py | 4 +-- edg/parts/microcontroller/EspCommon.py | 2 +- edg/parts/microcontroller/Lpc1549.py | 4 +-- edg/parts/microcontroller/Rp2040.py | 8 +++--- edg/parts/microcontroller/Stm32f103.py | 4 +-- edg/parts/microcontroller/Stm32f303.py | 4 +-- edg/parts/microcontroller/nRF52840.py | 4 +-- edg/parts/microcontroller/test_mcu_wrapper.py | 8 +++--- edg/parts/power/Batteries.py | 6 ++-- edg/parts/power/BatteryCharger_Mcp73831.py | 2 +- edg/parts/power/LedDriver_Tps92200.py | 4 +-- edg/parts/power/Ref30xx.py | 2 +- .../power/converter/AnalogDevices_Boost.py | 4 +-- edg/parts/power/converter/CustomBuckBoost.py | 8 ++++-- edg/parts/power/converter/DiodesInc_Boost.py | 6 ++-- edg/parts/power/converter/LinearRegulators.py | 22 +++++++-------- edg/parts/power/converter/Mp2722.py | 10 +++---- .../power/converter/TexasInstruments_Boost.py | 8 +++--- .../power/converter/TexasInstruments_Buck.py | 12 ++++---- .../converter/TexasInstruments_SwitchedCap.py | 4 +-- edg/parts/power/converter/Torex_Boost.py | 4 +-- edg/parts/power/gate_driver/Ncp3420.py | 2 +- edg/parts/power/gate_driver/Ucc27282.py | 2 +- edg/parts/power/motor/Bldc_Drv8313.py | 4 +-- edg/parts/power/motor/MotorDriver_Drv8833.py | 4 +-- edg/parts/power/motor/StepperDriver_A4988.py | 4 +-- edg/parts/sensor/Mag_Qmc5883.py | 4 +-- edg/parts/sensor/Rtc_Pcf2129.py | 4 +-- edg/util/__init__.py | 4 +-- examples/test_can_adapter.py | 2 +- examples/test_datalogger.py | 6 ++-- examples/test_deskcontroller.py | 2 +- examples/test_fcml.py | 8 +++--- examples/test_high_switch.py | 8 +++--- examples/test_iot_blinds.py | 2 +- examples/test_iot_display.py | 2 +- examples/test_iot_fan.py | 4 +-- examples/test_iot_iron.py | 4 +-- examples/test_iot_led_driver.py | 2 +- examples/test_iot_thermal_camera.py | 6 ++-- examples/test_multimeter.py | 6 ++-- examples/test_robotcrawler.py | 2 +- examples/test_tofarray.py | 2 +- examples/test_usb_source_measure.py | 10 +++---- 115 files changed, 352 insertions(+), 336 deletions(-) diff --git a/edg/abstract_parts/AnalogSwitch.py b/edg/abstract_parts/AnalogSwitch.py index edefd50fb..12091977f 100644 --- a/edg/abstract_parts/AnalogSwitch.py +++ b/edg/abstract_parts/AnalogSwitch.py @@ -130,7 +130,7 @@ def __init__(self) -> None: self.inputs = self.Port(Vector(AnalogSink.empty())) self.out = self.Port( AnalogSource( - voltage_out=self.inputs.hull(lambda x: x.link().voltage), + voltage=self.inputs.hull(lambda x: x.link().voltage), signal=self.inputs.hull(lambda x: x.link().signal), current_limits=self.device.analog_current_limits, # this device only, current draw propagated impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance), @@ -201,7 +201,7 @@ def generate(self) -> None: for elt in self.get(self.outputs.requested()): output = self.outputs.append_elt( AnalogSource( - voltage_out=self.input.link().voltage, + voltage=self.input.link().voltage, signal=self.input.link().signal, current_limits=self.device.analog_current_limits, # this device only, voltages propagated impedance=self.input.link().source_impedance + self.device.analog_on_resistance, diff --git a/edg/abstract_parts/Battery.py b/edg/abstract_parts/Battery.py index 526f7cdae..59672792b 100644 --- a/edg/abstract_parts/Battery.py +++ b/edg/abstract_parts/Battery.py @@ -13,6 +13,6 @@ def __init__(self, voltage: RangeLike, current: RangeLike = RangeExpr.ZERO, *, c self.capacity = self.ArgParameter(capacity) self.actual_capacity = self.Parameter(RangeExpr()) - self.require(self.pwr.voltage_out.within(voltage + self.gnd.link().voltage)) + self.require(self.pwr.voltage.within(voltage + self.gnd.link().voltage)) self.require(self.pwr.current_limits.contains(current)) self.require(self.actual_capacity.upper() >= capacity) diff --git a/edg/abstract_parts/Capacitor.py b/edg/abstract_parts/Capacitor.py index dd87e997f..81878526e 100644 --- a/edg/abstract_parts/Capacitor.py +++ b/edg/abstract_parts/Capacitor.py @@ -450,7 +450,7 @@ def __init__(self, capacitance: RangeLike, output_bias: RangeLike, *, exact_capa self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input]) self.output = self.Port( - AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=self.input.link().source_impedance), + AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=self.input.link().source_impedance), [Output], ) @@ -472,7 +472,7 @@ def contents(self) -> None: self.assign(self.input.impedance, self.output.link().sink_impedance) # assumed high frequency voltage_halfspan = (self.input.link().voltage.upper() - self.input.link().voltage.lower()) / 2 self.assign( - self.output.voltage_out, + self.output.voltage, (self.output_bias.lower() - voltage_halfspan, self.output_bias.upper() + voltage_halfspan), ) signal_halfspan = (self.input.link().signal.upper() - self.input.link().signal.lower()) / 2 diff --git a/edg/abstract_parts/FerriteBead.py b/edg/abstract_parts/FerriteBead.py index e9f4a8c86..75e1d3b92 100644 --- a/edg/abstract_parts/FerriteBead.py +++ b/edg/abstract_parts/FerriteBead.py @@ -119,7 +119,7 @@ def __init__(self, hf_impedance: RangeLike = RangeExpr.ALL, dc_resistance: Range self.pwr_in = self.Port(VoltageSink(voltage_limits=Range.all(), current_draw=RangeExpr()), [Power, Input]) self.pwr_out = self.Port( VoltageSource( - voltage_out=self.pwr_in.link().voltage, # ignore voltage drop + voltage=self.pwr_in.link().voltage, # ignore voltage drop current_limits=RangeExpr(), ), [Output], diff --git a/edg/abstract_parts/Fuse.py b/edg/abstract_parts/Fuse.py index 5c33e3c0d..25444c56d 100644 --- a/edg/abstract_parts/Fuse.py +++ b/edg/abstract_parts/Fuse.py @@ -89,7 +89,7 @@ def __init__(self, trip_current: RangeLike) -> None: [Power, Input], ) self.pwr_out = self.Port( - VoltageSource(voltage_out=self.pwr_in.link().voltage, current_limits=RangeExpr()), # ignore voltage drop + VoltageSource(voltage=self.pwr_in.link().voltage, current_limits=RangeExpr()), # ignore voltage drop [Output], ) diff --git a/edg/abstract_parts/Inductor.py b/edg/abstract_parts/Inductor.py index be95a99a8..96758b088 100644 --- a/edg/abstract_parts/Inductor.py +++ b/edg/abstract_parts/Inductor.py @@ -193,7 +193,7 @@ def __init__( self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Power, Input]) self.pwr_out = self.Port( VoltageSource( - voltage_out=self.pwr_in.link().voltage, + voltage=self.pwr_in.link().voltage, ), [Output], ) diff --git a/edg/abstract_parts/IoControllerInterfaceMixins.py b/edg/abstract_parts/IoControllerInterfaceMixins.py index 0ad1f4031..f9c1be16f 100644 --- a/edg/abstract_parts/IoControllerInterfaceMixins.py +++ b/edg/abstract_parts/IoControllerInterfaceMixins.py @@ -4,6 +4,7 @@ from ..electronics_interfaces import * from .IoController import BaseIoController, IoController +from ..util import deprecated_param_remap class IoControllerSpiPeripheral(BlockInterfaceMixin[BaseIoController]): @@ -145,8 +146,9 @@ def _generate_gnd_node(self) -> Ground: self.gnd_model = self.Block(DummyGround()) return self.gnd_model.io + @deprecated_param_remap(("voltage_out", "voltage")) def _generate_pwr_node( - self, voltage_out: RangeLike, current_limits: RangeLike + self, voltage: RangeLike, current_limits: RangeLike ) -> Union[VoltageSink, VoltageSource]: """Helper function that returns a power node, either directly taking the pwr port if available, or generating an internal voltage node and optionally connecting it to pwr_out (if used). @@ -159,7 +161,7 @@ def _generate_pwr_node( else: self.pwr_out_model = self.Block( DummyVoltageSource( - voltage_out=voltage_out, # tolerance is a guess + voltage=voltage, # tolerance is a guess current_limits=current_limits, ) ) diff --git a/edg/abstract_parts/Jumper.py b/edg/abstract_parts/Jumper.py index 43c2fdbe4..e8982cc5c 100644 --- a/edg/abstract_parts/Jumper.py +++ b/edg/abstract_parts/Jumper.py @@ -33,10 +33,10 @@ def contents(self) -> None: class VoltageJumper(TypedJumper, Block): def __init__(self) -> None: super().__init__() - self.input = self.Port(VoltageSink(current_draw=RangeExpr(), reverse_voltage_out=RangeExpr()), [Input]) + self.input = self.Port(VoltageSink(current_draw=RangeExpr(), reverse_voltage=RangeExpr()), [Input]) self.output = self.Port( VoltageSource( - voltage_out=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_draw + voltage=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_draw ), [Output], ) @@ -46,7 +46,7 @@ def contents(self) -> None: super().contents() self.device = self.Block(Jumper()) self.assign(self.input.current_draw, self.output.link().current_draw) - self.assign(self.input.reverse_voltage_out, self.output.link().reverse_voltage) + self.assign(self.input.reverse_voltage, self.output.link().reverse_voltage) self.connect(self.input.net, self.device.a) self.connect(self.output.net, self.device.b) @@ -56,7 +56,7 @@ def __init__(self) -> None: super().__init__() self.input = self.Port(DigitalSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( - DigitalSource(voltage_out=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds), + DigitalSource(voltage=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds), [Output], ) diff --git a/edg/abstract_parts/LinearRegulator.py b/edg/abstract_parts/LinearRegulator.py index b31779ae0..005608b5b 100644 --- a/edg/abstract_parts/LinearRegulator.py +++ b/edg/abstract_parts/LinearRegulator.py @@ -29,7 +29,7 @@ def contents(self) -> None: effective_output_voltage = self.output_voltage.intersect((0, self.pwr_in.link().voltage.upper())) self.gnd.init_from(Ground()) self.pwr_in.init_from(VoltageSink(current_draw=self.pwr_out.link().current_draw)) - self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) + self.pwr_out.init_from(VoltageSource(voltage=effective_output_voltage)) self.reset.init_from(DigitalSink()) @@ -52,12 +52,12 @@ def __init__(self) -> None: [Power, Input], ) self.pwr_out = self.Port( - VoltageSource(voltage_out=self.RangeExpr(), current_limits=RangeExpr()), # parameters set by subtype + VoltageSource(voltage=self.RangeExpr(), current_limits=RangeExpr()), # parameters set by subtype [Output], ) self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw + self.actual_quiescent_current) self.require( - self.pwr_out.voltage_out.lower() + self.actual_dropout.upper() <= self.pwr_in.link().voltage.lower(), + self.pwr_out.voltage.lower() + self.actual_dropout.upper() <= self.pwr_in.link().voltage.lower(), "excessive dropout", ) diff --git a/edg/abstract_parts/Resistor.py b/edg/abstract_parts/Resistor.py index 6610a8260..70e278d0f 100644 --- a/edg/abstract_parts/Resistor.py +++ b/edg/abstract_parts/Resistor.py @@ -301,7 +301,7 @@ def __init__(self, resistance: RangeLike) -> None: self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Power, Input]) self.pwr_out = self.Port( - VoltageSource(voltage_out=self.pwr_in.link().voltage), # ignore voltage drop + VoltageSource(voltage=self.pwr_in.link().voltage), # ignore voltage drop [Output], ) current_draw = self.pwr_out.link().current_draw.abs() @@ -424,7 +424,7 @@ def __init__(self, resistance: RangeLike) -> None: self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input]) self.output = self.Port( AnalogSource( - voltage_out=self.input.link().voltage, + voltage=self.input.link().voltage, signal=self.input.link().signal, impedance=self.input.link().source_impedance + self.res.actual_resistance, ), @@ -465,7 +465,7 @@ def __init__(self, resistance: RangeLike) -> None: self.input = self.Port(DigitalSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( DigitalSource( - voltage_out=self.input.link().voltage, + voltage=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds, ), [Output], @@ -521,7 +521,7 @@ def __init__(self, resistance: RangeLike) -> None: ) self.exterior = self.Port( DigitalBidir( - voltage_out=RangeExpr(), + voltage=RangeExpr(), current_draw=RangeExpr(), voltage_limits=RangeExpr(), current_limits=RangeExpr(), @@ -544,7 +544,7 @@ def __init__(self, resistance: RangeLike) -> None: self.connect(self.exterior.net, self.res.a) self.connect(self.interior.net, self.res.b) - self.assign(self.exterior.voltage_out, self.interior.link().voltage) + self.assign(self.exterior.voltage, self.interior.link().voltage) self.assign(self.exterior.current_draw, self.interior.link().current_draw) self.assign(self.exterior.voltage_limits, self.interior.link().voltage_limits) self.assign( diff --git a/edg/abstract_parts/SolidStateRelay.py b/edg/abstract_parts/SolidStateRelay.py index 6a9826fb4..89c9b858d 100644 --- a/edg/abstract_parts/SolidStateRelay.py +++ b/edg/abstract_parts/SolidStateRelay.py @@ -50,7 +50,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground(), [Common]) self.pwr_in = self.Port(VoltageSink(voltage_limits=RangeExpr(), current_draw=RangeExpr())) - self.pwr_out = self.Port(VoltageSource(voltage_out=self.pwr_in.link().voltage, current_limits=RangeExpr())) + self.pwr_out = self.Port(VoltageSource(voltage=self.pwr_in.link().voltage, current_limits=RangeExpr())) self.signal = self.Port(DigitalSink(current_draw=RangeExpr())) self.ic = self.Block(SolidStateRelay()) @@ -101,7 +101,7 @@ def __init__(self) -> None: self.ain = self.Port(AnalogSink(voltage_limits=RangeExpr(), impedance=RangeExpr())) self.aout = self.Port( AnalogSource( - voltage_out=self.ain.link().voltage, + voltage=self.ain.link().voltage, signal=self.ain.link().signal, current_limits=self.ic.load_current_limit, impedance=self.ain.link().source_impedance + self.ic.load_resistance, diff --git a/edg/abstract_parts/SwitchingVoltageRegulator.py b/edg/abstract_parts/SwitchingVoltageRegulator.py index 29a2b3686..58f8b6e3e 100644 --- a/edg/abstract_parts/SwitchingVoltageRegulator.py +++ b/edg/abstract_parts/SwitchingVoltageRegulator.py @@ -57,7 +57,7 @@ class BuckConverter(SwitchingVoltageRegulator): def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) - self.require(self.pwr_out.voltage_out.upper() <= self.pwr_in.voltage_limits.upper()) + self.require(self.pwr_out.voltage.upper() <= self.pwr_in.voltage_limits.upper()) @abstract_block_default(lambda: IdealBuckConverter) @@ -79,7 +79,7 @@ def contents(self) -> None: current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) - self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) + self.pwr_out.init_from(VoltageSource(voltage=effective_output_voltage)) self.reset.init_from(DigitalSink()) @@ -89,7 +89,7 @@ class BoostConverter(SwitchingVoltageRegulator): def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) - self.require(self.pwr_out.voltage_out.lower() >= self.pwr_in.voltage_limits.lower()) + self.require(self.pwr_out.voltage.lower() >= self.pwr_in.voltage_limits.lower()) @abstract_block_default(lambda: IdealBoostConverter) @@ -111,7 +111,7 @@ def contents(self) -> None: current_draw=effective_output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) - self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage)) + self.pwr_out.init_from(VoltageSource(voltage=effective_output_voltage)) self.reset.init_from(DigitalSink()) diff --git a/edg/abstract_parts/VoltageRegulator.py b/edg/abstract_parts/VoltageRegulator.py index c7299335a..b73858c6b 100644 --- a/edg/abstract_parts/VoltageRegulator.py +++ b/edg/abstract_parts/VoltageRegulator.py @@ -33,7 +33,7 @@ def contents(self) -> None: self.description = DescriptionString( "output voltage: ", - DescriptionString.FormatUnits(self.pwr_out.voltage_out, "V"), + DescriptionString.FormatUnits(self.pwr_out.voltage, "V"), " of spec: ", DescriptionString.FormatUnits(self.output_voltage, "V"), "\n", @@ -41,7 +41,7 @@ def contents(self) -> None: DescriptionString.FormatUnits(self.pwr_in.link().voltage, "V"), ) - self.require(self.pwr_out.voltage_out.within(self.output_voltage), "Output voltage must be within spec") + self.require(self.pwr_out.voltage.within(self.output_voltage), "Output voltage must be within spec") @non_library @@ -82,5 +82,5 @@ def contents(self) -> None: current_draw=self.output_voltage / self.pwr_in.link().voltage * self.pwr_out.link().current_draw ) ) - self.pwr_out.init_from(VoltageSource(voltage_out=self.output_voltage)) + self.pwr_out.init_from(VoltageSource(voltage=self.output_voltage)) self.reset.init_from(DigitalSink()) diff --git a/edg/abstract_parts/ZenerDiode.py b/edg/abstract_parts/ZenerDiode.py index f089b27fa..71bba05c6 100644 --- a/edg/abstract_parts/ZenerDiode.py +++ b/edg/abstract_parts/ZenerDiode.py @@ -100,7 +100,7 @@ def __init__(self, voltage: RangeLike): self.signal_in = self.Port(AnalogSink(), [Input]) self.signal_out = self.Port( AnalogSource( - voltage_out=self.signal_in.link().voltage.intersect( + voltage=self.signal_in.link().voltage.intersect( self.gnd.link().voltage + (0, self.diode.actual_zener_voltage.upper()) ), signal=self.signal_in.link().signal, diff --git a/edg/abstract_parts/test_pinmappable.py b/edg/abstract_parts/test_pinmappable.py index 563f1191a..99222f464 100644 --- a/edg/abstract_parts/test_pinmappable.py +++ b/edg/abstract_parts/test_pinmappable.py @@ -289,9 +289,7 @@ def test_assign_bundle_delegating_badspec(self) -> None: def test_assign_bundle_delegating_fixed(self) -> None: dio_model = DigitalBidir() - dio_model_tx = DigitalBidir( - voltage_out=3.3 * Volt(tol=0.01), - ) + dio_model_tx = DigitalBidir(voltage=3.3 * Volt(tol=0.01)) dio_model_rx = DigitalBidir(current_draw=1 * mAmp(tol=0.01)) ain_model = AnalogSink() allocated = PinMapUtil( @@ -308,8 +306,8 @@ def test_assign_bundle_delegating_fixed(self) -> None: self.assertEqual(allocated[0].pin, {"tx": ("3", "3"), "rx": ("1", "1")}) assert isinstance(allocated[0].port_model, UartPort) - self.assertTrue(allocated[0].port_model.tx.voltage_out.initializer is not None) - self.assertTrue(allocated[0].port_model.tx.voltage_out.initializer is dio_model_tx.voltage_out.initializer) + self.assertTrue(allocated[0].port_model.tx.voltage.initializer is not None) + self.assertTrue(allocated[0].port_model.tx.voltage.initializer is dio_model_tx.voltage.initializer) self.assertTrue(allocated[0].port_model.rx.current_draw.initializer is not None) self.assertTrue(allocated[0].port_model.rx.current_draw.initializer is dio_model_rx.current_draw.initializer) diff --git a/edg/circuits/BoostConverterPowerPath.py b/edg/circuits/BoostConverterPowerPath.py index f353b718d..8d72cc0c8 100644 --- a/edg/circuits/BoostConverterPowerPath.py +++ b/edg/circuits/BoostConverterPowerPath.py @@ -214,7 +214,7 @@ def generate(self) -> None: self.switch, self.inductor.b.adapt_to( VoltageSource( - voltage_out=self.output_voltage, + voltage=self.output_voltage, current_limits=BuckConverterPowerPath._ilim_expr( self.inductor.actual_current_rating, self.sw_current_limits, self.actual_inductor_current_ripple ) diff --git a/edg/circuits/BootstrapCapacitor.py b/edg/circuits/BootstrapCapacitor.py index c2f2a00b0..3f1163420 100644 --- a/edg/circuits/BootstrapCapacitor.py +++ b/edg/circuits/BootstrapCapacitor.py @@ -16,14 +16,12 @@ def __init__(self, capacitance: RangeLike): self.neg = self.Port(VoltageSink()) self.pos = self.Port( - VoltageSource( - voltage_out=RangeExpr(), reverse_voltage_limits=RangeExpr.ALL, reverse_current_draw=(0, 0) * Amp - ) + VoltageSource(voltage=RangeExpr(), reverse_voltage_limits=RangeExpr.ALL, reverse_current_draw=(0, 0) * Amp) ) boost_voltage = self.pos.link().reverse_voltage - self.neg.link().voltage.lower() self.cap = self.Block(Capacitor(capacitance=capacitance, voltage=boost_voltage)) - self.assign(self.pos.voltage_out, self.neg.link().voltage + boost_voltage) + self.assign(self.pos.voltage, self.neg.link().voltage + boost_voltage) self.connect(self.pos.net, self.cap.pos) self.connect(self.neg.net, self.cap.neg) diff --git a/edg/circuits/BuckBoostConverterPowerPath.py b/edg/circuits/BuckBoostConverterPowerPath.py index 71a7d64aa..77d1fbc2a 100644 --- a/edg/circuits/BuckBoostConverterPowerPath.py +++ b/edg/circuits/BuckBoostConverterPowerPath.py @@ -138,7 +138,7 @@ def generate(self) -> None: self.switch_out, self.inductor.b.adapt_to( VoltageSource( - voltage_out=self.output_voltage, + voltage=self.output_voltage, current_limits=BuckConverterPowerPath._ilim_expr( self.inductor.actual_current_rating, self.sw_current_limits, self.actual_inductor_current_ripple ) diff --git a/edg/circuits/BuckConverterPowerPath.py b/edg/circuits/BuckConverterPowerPath.py index 112f45539..34bb45d5c 100644 --- a/edg/circuits/BuckConverterPowerPath.py +++ b/edg/circuits/BuckConverterPowerPath.py @@ -274,7 +274,7 @@ def generate(self) -> None: self.pwr_out, self.inductor.b.adapt_to( VoltageSource( - voltage_out=self.output_voltage, + voltage=self.output_voltage, current_limits=self._ilim_expr( self.inductor.actual_current_rating, self.sw_current_limits, self.actual_inductor_current_ripple ) diff --git a/edg/circuits/ControlCircuits.py b/edg/circuits/ControlCircuits.py index 1615bdfd6..f44a720c1 100644 --- a/edg/circuits/ControlCircuits.py +++ b/edg/circuits/ControlCircuits.py @@ -116,7 +116,7 @@ def contents(self) -> None: conversions={ "r1.1": AnalogSink(impedance=self.r1.actual_resistance), # TODO very simplified and probably very wrong # these model the opamp in- node - "r1.2": AnalogSource(voltage_out=self.amp.out.voltage_out, impedance=self.r1.actual_resistance), + "r1.2": AnalogSource(voltage=self.amp.out.voltage, impedance=self.r1.actual_resistance), "r2.1": AnalogSink(), "c2.2": AnalogSink(), # these model the opamp out node diff --git a/edg/circuits/DigitalAmplifiers.py b/edg/circuits/DigitalAmplifiers.py index 8db96edae..ab552d536 100644 --- a/edg/circuits/DigitalAmplifiers.py +++ b/edg/circuits/DigitalAmplifiers.py @@ -26,7 +26,7 @@ def __init__( self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Power]) self.control = self.Port(DigitalSink(), [Input]) - self.pwr_out = self.Port(VoltageSource(voltage_out=self.pwr_in.link().voltage), [Output]) + self.pwr_out = self.Port(VoltageSource(voltage=self.pwr_in.link().voltage), [Output]) @override def contents(self) -> None: @@ -135,7 +135,7 @@ def generate(self) -> None: conversions: Dict[str, HasPassivePort] = { "pwr": VoltageSink(current_draw=self.output.link().current_draw), "output": VoltageSource( - voltage_out=self.pwr.link().voltage, + voltage=self.pwr.link().voltage, current_limits=self.drv.actual_drain_current_rating, ), "control": DigitalSink(), # TODO model pullup resistor current diff --git a/edg/circuits/LevelShifter.py b/edg/circuits/LevelShifter.py index 3889d57f2..8a74928b5 100644 --- a/edg/circuits/LevelShifter.py +++ b/edg/circuits/LevelShifter.py @@ -51,12 +51,12 @@ def generate(self) -> None: if self.get(self.src_hint) == "lv": # LV is source, HV model is incomplete lv_io_model = DigitalBidir( - voltage_out=self.lv_pwr.link().voltage, # this is not driving, effectively only a pullup + voltage=self.lv_pwr.link().voltage, # this is not driving, effectively only a pullup output_thresholds=self.lv_pwr.link().voltage.hull(-float("inf")), ) else: # HV model is complete, can use its thresholds lv_io_model = DigitalBidir( - voltage_out=( + voltage=( self.lv_pwr.link().voltage.lower(), self.lv_pwr.link().voltage.upper().min(self.hv_io.link().voltage.upper()), ), @@ -68,12 +68,12 @@ def generate(self) -> None: if self.get(self.src_hint) == "hv": # HV is source, LV model is incomplete hv_io_model = DigitalBidir( - voltage_out=self.hv_pwr.link().voltage, # this is not driving, effectively only a pullup + voltage=self.hv_pwr.link().voltage, # this is not driving, effectively only a pullup output_thresholds=self.hv_pwr.link().voltage.hull(-float("inf")), ) else: # HV model is complete, can use its thresholds hv_io_model = DigitalBidir( - voltage_out=self.hv_pwr.link().voltage.hull(self.lv_io.link().voltage.lower()), + voltage=self.hv_pwr.link().voltage.hull(self.lv_io.link().voltage.lower()), output_thresholds=self.hv_pwr.link().voltage.hull(self.lv_io.link().voltage.lower()), ) diff --git a/edg/circuits/OpampCircuits.py b/edg/circuits/OpampCircuits.py index 49b2f435b..907d29c79 100644 --- a/edg/circuits/OpampCircuits.py +++ b/edg/circuits/OpampCircuits.py @@ -159,7 +159,7 @@ def generate(self) -> None: reference_node = self.gnd reference_range = self.gnd.link().voltage - input_signal_range = self.amp.out.voltage_out.intersect(self.input.link().signal - reference_range) + input_signal_range = self.amp.out.voltage.intersect(self.input.link().signal - reference_range) output_range = input_signal_range * self.actual_amplification + reference_range # TODO tolerances can cause the range to be much larger than actual, so bound it to avoid false-positives self.forced = self.Block(ForcedAnalogSignal(self.amp.out.signal.intersect(output_range))) @@ -169,7 +169,7 @@ def generate(self) -> None: conversions={ "r1.1": AnalogSink(impedance=self.r1.actual_resistance + self.r2.actual_resistance), "r1.2": AnalogSource( # this models the entire node - voltage_out=self.amp.out.voltage_out, + voltage=self.amp.out.voltage, impedance=1 / (1 / self.r1.actual_resistance + 1 / self.r2.actual_resistance), ), "r2.1": AnalogSink(), # ideal @@ -322,9 +322,9 @@ def generate(self) -> None: impedance=self.r1.actual_resistance + self.rf.actual_resistance ), "r1.2": AnalogSource( # combined R1 and Rf resistance - voltage_out=ResistiveDivider.divider_output( + voltage=ResistiveDivider.divider_output( self.input_negative.link().voltage, - self.amp.out.voltage_out, + self.amp.out.voltage, ResistiveDivider.divider_ratio(self.r1.actual_resistance, self.rf.actual_resistance), ), impedance=1 / (1 / self.r1.actual_resistance + 1 / self.rf.actual_resistance), @@ -335,7 +335,7 @@ def generate(self) -> None: ), "r2.1": AnalogSink(impedance=self.r2.actual_resistance + self.rg.actual_resistance), "r2.2": AnalogSource( # combined R2 and Rg resistance - voltage_out=ResistiveDivider.divider_output( + voltage=ResistiveDivider.divider_output( self.input_positive.link().voltage, output_neg_voltage, ResistiveDivider.divider_ratio(self.r2.actual_resistance, self.rg.actual_resistance), @@ -418,7 +418,7 @@ def contents(self) -> None: conversions={ "r.1": AnalogSink(impedance=self.r.actual_resistance), # TODO very simplified and probably very wrong "c.1": AnalogSink(), # TODO impedance of the feedback circuit? - "r.2": AnalogSource(voltage_out=self.amp.out.voltage_out, impedance=self.r.actual_resistance), + "r.2": AnalogSource(voltage=self.amp.out.voltage, impedance=self.r.actual_resistance), "c.2": AnalogSink(), }, ) diff --git a/edg/circuits/OpampCurrentSensor.py b/edg/circuits/OpampCurrentSensor.py index 69e2629ce..bf6445904 100644 --- a/edg/circuits/OpampCurrentSensor.py +++ b/edg/circuits/OpampCurrentSensor.py @@ -36,7 +36,7 @@ def contents(self) -> None: output_swing = self.pwr_out.link().current_draw * self.sense.actual_resistance * self.amp.actual_ratio self.force_signal = self.Block(ForcedAnalogSignal(output_swing + self.ref.link().signal)) self.connect(self.amp.output, self.force_signal.signal_in) - self.connect(self.force_signal.signal, self.out) + self.connect(self.force_signal.signal_out, self.out) @override def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]: diff --git a/edg/circuits/PassiveFilters.py b/edg/circuits/PassiveFilters.py index bdfa70f7b..f17ac8633 100644 --- a/edg/circuits/PassiveFilters.py +++ b/edg/circuits/PassiveFilters.py @@ -78,7 +78,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): super().__init__() self.input = self.Port(AnalogSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( - AnalogSource(voltage_out=self.input.link().voltage, signal=self.input.link().signal), [Output] + AnalogSource(voltage=self.input.link().voltage, signal=self.input.link().signal), [Output] ) self.assign(self.input.current_draw, self.output.link().current_draw) @@ -101,7 +101,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.input = self.Port(DigitalSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( DigitalSource( - voltage_out=self.input.link().voltage, + voltage=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds, ), [Output], @@ -156,7 +156,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.input = self.Port(DigitalSink(current_draw=RangeExpr()), [Input]) self.output = self.Port( AnalogSource( - voltage_out=self.input.link().voltage, + voltage=self.input.link().voltage, signal=self.input.link().voltage, impedance=impedance, # TODO use selected resistance from RC filter ), @@ -185,14 +185,14 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.inp = self.Port(AnalogSink(impedance=RangeExpr(), current_draw=RangeExpr())) self.outn = self.Port( AnalogSource( - voltage_out=self.inn.link().voltage, + voltage=self.inn.link().voltage, signal=self.inn.link().signal, impedance=RangeExpr(), ) ) self.outp = self.Port( AnalogSource( - voltage_out=self.inp.link().voltage, + voltage=self.inp.link().voltage, signal=self.inp.link().signal, impedance=RangeExpr(), ) diff --git a/edg/circuits/PowerCircuits.py b/edg/circuits/PowerCircuits.py index 490eb2361..865d7b6e5 100644 --- a/edg/circuits/PowerCircuits.py +++ b/edg/circuits/PowerCircuits.py @@ -108,7 +108,7 @@ def contents(self) -> None: # to avoid tolerance stackup, model the switch node as a static voltage self.connect(self.low_fet.drain, self.high_fet.source) - self.connect(self.low_fet.drain.adapt_to(VoltageSource(voltage_out=self.pwr.link().voltage)), self.out) + self.connect(self.low_fet.drain.adapt_to(VoltageSource(voltage=self.pwr.link().voltage)), self.out) self.connect(self.out.as_ground((0, 0) * Amp), self.driver.high_gnd) # TODO model driver current self.assign( @@ -261,7 +261,7 @@ def contents(self) -> None: self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), conversions={ "pwr_in": VoltageSink(current_draw=self.pwr_out.link().current_draw + div_current_draw), - "pwr_out": VoltageSource(voltage_out=self.pwr_in.link().voltage), + "pwr_out": VoltageSource(voltage=self.pwr_in.link().voltage), "control": DigitalSink(), "gnd": Ground(), }, diff --git a/edg/circuits/PowerConditioning.py b/edg/circuits/PowerConditioning.py index f218c7ae5..61caffeb8 100644 --- a/edg/circuits/PowerConditioning.py +++ b/edg/circuits/PowerConditioning.py @@ -18,7 +18,7 @@ def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: self.pwr_in_diode = self.Port(VoltageSink(current_draw=RangeExpr())) # low-priority source self.pwr_out = self.Port( VoltageSource( # use the spec voltage drop to avoid circular dependencies downstream - voltage_out=self.pwr_in.link().voltage.hull(self.pwr_in_diode.link().voltage - voltage_drop), + voltage=self.pwr_in.link().voltage.hull(self.pwr_in_diode.link().voltage - voltage_drop), ) ) @@ -49,7 +49,7 @@ def __init__(self, voltage_drop: RangeLike = (0, 0.6) * Volt) -> None: self.voltage_drop = self.ArgParameter(voltage_drop) self.pwr_ins = self.Port(Vector(VoltageSink.empty())) - self.pwr_out = self.Port(VoltageSource(voltage_out=RangeExpr())) + self.pwr_out = self.Port(VoltageSource(voltage=RangeExpr())) self.generator_param(self.pwr_ins.requested()) @override @@ -58,7 +58,7 @@ def generate(self) -> None: input_hull = self.pwr_ins.map_extract(lambda pwr_in: pwr_in.link().voltage).hull() # use the spec voltage drop to avoid circular dependencies downstream - self.assign(self.pwr_out.voltage_out, input_hull - self.voltage_drop) + self.assign(self.pwr_out.voltage, input_hull - self.voltage_drop) requested = self.get(self.pwr_ins.requested()) assert len(requested) > 0, "power inputs required" @@ -69,7 +69,7 @@ def generate(self) -> None: pwr_in = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_draw), name) self.diodes[name] = diode = self.Block( Diode( - reverse_voltage=(0, self.pwr_out.voltage_out.upper() - pwr_in.link().voltage.lower()), + reverse_voltage=(0, self.pwr_out.voltage.upper() - pwr_in.link().voltage.lower()), current=self.pwr_out.link().current_draw, voltage_drop=self.voltage_drop, ) @@ -138,7 +138,7 @@ def contents(self) -> None: "pwr_hi": VoltageSink(current_draw=output_current_draw), "pwr_lo": VoltageSink(current_draw=output_current_draw), "pwr_out": VoltageSource( - voltage_out=self.pwr_lo.link().voltage.hull( + voltage=self.pwr_lo.link().voltage.hull( # use the spec voltage drop since using the actual voltage drop causes a circular dependency # (where current depends on voltage, but the diode voltage drop depends on the diode selection # which depends on the current through) @@ -205,7 +205,7 @@ def contents(self) -> None: current_draw=output_current_draw, ), "pwr_out": VoltageSource( - voltage_out=self.pwr_in.link().voltage, + voltage=self.pwr_in.link().voltage, ), "gnd": Ground(), }, @@ -280,11 +280,11 @@ def contents(self) -> None: conversions={ "pwr_in": VoltageSink( current_draw=batt_current, - reverse_voltage_out=self.pwr_out.link().reverse_voltage, + reverse_voltage=self.pwr_out.link().reverse_voltage, reverse_current_limits=RangeExpr.ALL, ), "pwr_out": VoltageSource( - voltage_out=batt_voltage, + voltage=batt_voltage, reverse_voltage_limits=self.pwr_in.link().reverse_voltage_limits, reverse_current_draw=self.pwr_in.link().reverse_current_draw, ), @@ -384,13 +384,13 @@ def contents(self) -> None: current_draw=self.pwr_out.link().current_draw, ), "pwr_out": VoltageSource( - voltage_out=self.pwr_in.link().voltage, + voltage=self.pwr_in.link().voltage, ), "control": DigitalSink(), # TODO more modeling here? "gnd": Ground(), "btn_out": DigitalSource.low_from_supply(self.gnd), "btn_in": DigitalBidir( - voltage_out=self.gnd.link().voltage, + voltage=self.gnd.link().voltage, output_thresholds=(self.gnd.link().voltage.upper(), float("inf")), pullup_capable=True, ), diff --git a/edg/circuits/ResistiveDivider.py b/edg/circuits/ResistiveDivider.py index 5f6fd36f4..00e176786 100644 --- a/edg/circuits/ResistiveDivider.py +++ b/edg/circuits/ResistiveDivider.py @@ -173,7 +173,7 @@ def __init__(self, impedance: RangeLike) -> None: ) self.output = self.Port( AnalogSource( - voltage_out=output_voltage, + voltage=output_voltage, signal=output_voltage, impedance=self.div.actual_impedance, ), @@ -272,7 +272,7 @@ def __init__(self, ratio: RangeLike, impedance: RangeLike) -> None: self.input.link().voltage, self.gnd.link().voltage, self.div.actual_ratio ) self.output = self.Port( - AnalogSource(voltage_out=output_voltage, signal=output_voltage, impedance=self.div.actual_impedance), + AnalogSource(voltage=output_voltage, signal=output_voltage, impedance=self.div.actual_impedance), [Output], ) self.assign(self.input.current_draw, self.output.link().current_draw) diff --git a/edg/circuits/ResistiveSensor.py b/edg/circuits/ResistiveSensor.py index cf5dfe086..e30438a6f 100644 --- a/edg/circuits/ResistiveSensor.py +++ b/edg/circuits/ResistiveSensor.py @@ -17,7 +17,7 @@ def __init__(self, resistance_range: RangeLike, fixed_resistance: RangeLike) -> self.input = self.Port(VoltageSink(current_draw=RangeExpr()), [Power]) self.output = self.Port( - AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr()), [Output] + AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr()), [Output] ) self.gnd = self.Port(Ground(), [Common]) @@ -35,7 +35,7 @@ def contents(self) -> None: output_voltage = ResistiveDivider.divider_output( self.input.link().voltage, self.gnd.link().voltage, self.actual_ratio ) - self.assign(self.output.voltage_out, output_voltage) + self.assign(self.output.voltage, output_voltage) self.assign(self.output.signal, output_voltage) self.assign(self.output.impedance, self.actual_impedance) self.connect(self.output.net, self.top.b, self.bot.pins.request("1")) diff --git a/edg/circuits/SwitchMatrix.py b/edg/circuits/SwitchMatrix.py index f2b63ce25..b22fa421c 100644 --- a/edg/circuits/SwitchMatrix.py +++ b/edg/circuits/SwitchMatrix.py @@ -27,7 +27,7 @@ def contents(self) -> None: self.col.init_from( DigitalSource( # diode anode, externally pulled, driven to col by switch closure - voltage_out=self.row.link().voltage.lower() + voltage=self.row.link().voltage.lower() + self.voltage_drop, # use spec to avoid circular dependency output_thresholds=(self.row.link().voltage + self.voltage_drop).hull(float("inf")), low_driver=True, diff --git a/edg/circuits/UsbBitBang.py b/edg/circuits/UsbBitBang.py index f75b5cc51..a2bd8def6 100644 --- a/edg/circuits/UsbBitBang.py +++ b/edg/circuits/UsbBitBang.py @@ -18,7 +18,7 @@ def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir: These are basically the semantics of a DigitalBidir bridge. TODO: unify code w/ DigitalBidir bridge?""" return DigitalBidir( - voltage_out=link_port.link().voltage, + voltage=link_port.link().voltage, current_draw=link_port.link().current_draw, voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits, diff --git a/edg/circuits/VoltageClamping.py b/edg/circuits/VoltageClamping.py index e73b6bead..151a3f3df 100644 --- a/edg/circuits/VoltageClamping.py +++ b/edg/circuits/VoltageClamping.py @@ -32,7 +32,7 @@ def __init__( self.signal_in = self.Port(AnalogSink(), [Input]) self.signal_out = self.Port( AnalogSource( - voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target), + voltage=self.signal_in.link().voltage.intersect(self.clamp_target), signal=self.signal_in.link().signal, impedance=RangeExpr(), ), @@ -92,7 +92,7 @@ def __init__( self.signal_in = self.Port(DigitalSink(current_draw=RangeExpr()), [Input]) self.signal_out = self.Port( DigitalSource( - voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target), + voltage=self.signal_in.link().voltage.intersect(self.clamp_target), output_thresholds=self.signal_in.link().output_thresholds, ), [Output], diff --git a/edg/circuits/test_diodemerge.py b/edg/circuits/test_diodemerge.py index 58c554b73..214762d40 100644 --- a/edg/circuits/test_diodemerge.py +++ b/edg/circuits/test_diodemerge.py @@ -10,8 +10,8 @@ class DiodeMergeTestTop(DesignTop): def __init__(self) -> None: super().__init__() self.dut = self.Block(DiodePowerMerge(voltage_drop=(0, 1) * Volt)) - self.srca = self.Block(DummyVoltageSource(voltage_out=(12, 14) * Volt)).connected(self.dut.pwr_ins.request()) - self.srcb = self.Block(DummyVoltageSource(voltage_out=(4, 5) * Volt)).connected(self.dut.pwr_ins.request()) + self.srca = self.Block(DummyVoltageSource(voltage=(12, 14) * Volt)).connected(self.dut.pwr_ins.request()) + self.srcb = self.Block(DummyVoltageSource(voltage=(4, 5) * Volt)).connected(self.dut.pwr_ins.request()) self.sink = self.Block(DummyVoltageSink(current_draw=(0.5, 1.5) * Amp)).connected(self.dut.pwr_out) @override @@ -30,7 +30,7 @@ class DiodeMergeTestCase(unittest.TestCase): def test_diode_merge(self) -> None: compiled = ScalaCompiler.compile(DiodeMergeTestTop) - self.assertEqual(compiled.get_value(["dut", "pwr_out", "voltage_out"]), Range(3.0, 14.0)) + self.assertEqual(compiled.get_value(["dut", "pwr_out", "voltage"]), Range(3.0, 14.0)) self.assertEqual(compiled.get_value(["dut", "pwr_ins", "0", "current_draw"]), Range(0.5, 1.5)) self.assertEqual(compiled.get_value(["dut", "pwr_ins", "1", "current_draw"]), Range(0.5, 1.5)) self.assertEqual(compiled.get_value(["dut", "diodes[0]", "fp_footprint"]), "Diode_SMD:D_SOD-123") diff --git a/edg/circuits/test_power_circuits.py b/edg/circuits/test_power_circuits.py index 1f15a0f9c..8d6dd5f4e 100644 --- a/edg/circuits/test_power_circuits.py +++ b/edg/circuits/test_power_circuits.py @@ -13,9 +13,9 @@ def __init__(self) -> None: self.dut = self.Block(RampLimiter()) self.dummygnd = self.Block(DummyGround()).connected(self.dut.gnd) - self.dummyin = self.Block(DummyVoltageSource(voltage_out=12 * Volt(tol=0))).connected(self.dut.pwr_in) + self.dummyin = self.Block(DummyVoltageSource(voltage=12 * Volt(tol=0))).connected(self.dut.pwr_in) self.dummyout = self.Block(DummyVoltageSink(current_draw=1 * Amp(tol=0))).connected(self.dut.pwr_out) - self.dummyctl = self.Block(DummyDigitalSource(voltage_out=3.3 * Volt(tol=0))).connected(self.dut.control) + self.dummyctl = self.Block(DummyDigitalSource(voltage=3.3 * Volt(tol=0))).connected(self.dut.control) @override def refinements(self) -> Refinements: diff --git a/edg/electronics_interfaces/CircuitPackingBlock.py b/edg/electronics_interfaces/CircuitPackingBlock.py index 3980fcc01..370ec720c 100644 --- a/edg/electronics_interfaces/CircuitPackingBlock.py +++ b/edg/electronics_interfaces/CircuitPackingBlock.py @@ -43,7 +43,7 @@ class PackedGround(GeneratorBlock): def __init__(self) -> None: super().__init__() self.gnd_ins = self.Port(Vector(Ground.empty())) - self.gnd_out = self.Port(GroundReference(voltage_out=RangeExpr())) + self.gnd_out = self.Port(GroundReference(voltage=RangeExpr())) self.generator_param(self.gnd_ins.requested()) @override @@ -56,7 +56,7 @@ def generate(self) -> None: in_port = self.gnd_ins.append_elt(Ground(), in_request) self.connect(in_port.net, self.packed.elts.request(in_request)) self.connect(self.packed.merged, self.gnd_out.net) - self.assign(self.gnd_out.voltage_out, self.gnd_ins.hull(lambda x: x.link().voltage)) + self.assign(self.gnd_out.voltage, self.gnd_ins.hull(lambda x: x.link().voltage)) class PackedVoltageSource(GeneratorBlock): @@ -67,7 +67,7 @@ class PackedVoltageSource(GeneratorBlock): def __init__(self) -> None: super().__init__() self.pwr_ins = self.Port(Vector(VoltageSink.empty())) - self.pwr_out = self.Port(VoltageSource(voltage_out=RangeExpr())) + self.pwr_out = self.Port(VoltageSource(voltage=RangeExpr())) self.generator_param(self.pwr_ins.requested()) @override @@ -83,4 +83,4 @@ def generate(self) -> None: ) self.connect(in_port.net, self.packed.elts.request(in_request)) self.connect(self.packed.merged, self.pwr_out.net) - self.assign(self.pwr_out.voltage_out, self.pwr_ins.hull(lambda x: x.link().voltage)) + self.assign(self.pwr_out.voltage, self.pwr_ins.hull(lambda x: x.link().voltage)) diff --git a/edg/electronics_interfaces/CrystalPort.py b/edg/electronics_interfaces/CrystalPort.py index ef1be3b18..16914ce25 100644 --- a/edg/electronics_interfaces/CrystalPort.py +++ b/edg/electronics_interfaces/CrystalPort.py @@ -1,6 +1,8 @@ +from deprecated import deprecated from typing_extensions import override from ..electronics_model import * +from ..util import deprecated_param_remap class CrystalLink(Link): @@ -9,7 +11,7 @@ def __init__(self) -> None: self.driver = self.Port(CrystalDriver()) self.crystal = self.Port(CrystalPort()) - self.drive_voltage = self.Parameter(RangeExpr(self.driver.voltage_out)) + self.drive_voltage = self.Parameter(RangeExpr(self.driver.voltage)) self.frequency = self.Parameter(RangeExpr(self.crystal.frequency)) @override @@ -35,10 +37,16 @@ def __init__(self, frequency: RangeLike = RangeExpr.ZERO) -> None: class CrystalDriver(Port[CrystalLink]): link_type = CrystalLink - def __init__(self, frequency_limits: RangeLike = RangeExpr.ALL, voltage_out: RangeLike = RangeExpr.ZERO) -> None: + @deprecated_param_remap(("voltage_out", "voltage")) + def __init__(self, frequency_limits: RangeLike = RangeExpr.ALL, voltage: RangeLike = RangeExpr.ZERO) -> None: super().__init__() - self.voltage_out = self.Parameter(RangeExpr(voltage_out)) + self.voltage = self.Parameter(RangeExpr(voltage)) self.xtal_in = self.Port(Passive()) self.xtal_out = self.Port(Passive()) self.frequency_limits = self.Parameter(RangeExpr(frequency_limits)) + + @property + @deprecated("use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage diff --git a/edg/electronics_interfaces/DigitalPorts.py b/edg/electronics_interfaces/DigitalPorts.py index 7de8956bc..8a6d6bf01 100644 --- a/edg/electronics_interfaces/DigitalPorts.py +++ b/edg/electronics_interfaces/DigitalPorts.py @@ -183,7 +183,7 @@ def __init__(self) -> None: self.inner_link = self.Port( DigitalSource( current_limits=RangeExpr.ALL, - voltage_out=RangeExpr(), + voltage=RangeExpr(), output_thresholds=RangeExpr(), pullup_capable=False, pulldown_capable=False, # don't create a loop @@ -291,7 +291,7 @@ def __init__(self) -> None: super().__init__() self.outer_port = self.Port( - DigitalSource(voltage_out=RangeExpr(), current_limits=RangeExpr(), output_thresholds=RangeExpr()) + DigitalSource(voltage=RangeExpr(), current_limits=RangeExpr(), output_thresholds=RangeExpr()) ) # Here we ignore the voltage_limits of the inner port, instead relying on the main link to handle it @@ -329,7 +329,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Port(DigitalSink(current_draw=RangeExpr())) # otherwise ideal self.dst = self.Port( - VoltageSource(voltage_out=(self.src.link().output_thresholds.upper(), self.src.link().voltage.upper())) + VoltageSource(voltage=(self.src.link().output_thresholds.upper(), self.src.link().voltage.upper())) ) self.assign(self.src.current_draw, self.dst.link().current_draw) self.connect(self.src.net, self.dst.net) @@ -357,9 +357,7 @@ def from_supply( else: output_threshold = (GroundLink._voltage_range(neg).upper(), VoltageLink._voltage_range(pos).lower()) - return DigitalSource( - voltage_out=supply_range, current_limits=current_limits, output_thresholds=output_threshold - ) + return DigitalSource(voltage=supply_range, current_limits=current_limits, output_thresholds=output_threshold) @staticmethod def from_bidir(model: DigitalBidir) -> DigitalSource: @@ -420,7 +418,7 @@ def low_from_supply(neg: Port[GroundLink], *, current_limits: RangeLike = RangeE def high_from_supply(pos: Port[VoltageLink], *, current_limits: RangeLike = RangeExpr.ALL) -> DigitalSource: """Source-only digital source""" return DigitalSource( - voltage_out=pos.link().voltage, + voltage=pos.link().voltage, current_limits=current_limits, output_thresholds=(-float("inf"), pos.link().voltage.lower()), high_driver=True, @@ -432,7 +430,7 @@ def high_from_supply(pos: Port[VoltageLink], *, current_limits: RangeLike = Rang @staticmethod def pulldown_from_supply(neg: Port[GroundLink]) -> DigitalSource: return DigitalSource( - voltage_out=neg.link().voltage, + voltage=neg.link().voltage, output_thresholds=(neg.link().voltage.upper(), float("inf")), high_driver=False, low_driver=False, @@ -443,7 +441,7 @@ def pulldown_from_supply(neg: Port[GroundLink]) -> DigitalSource: @staticmethod def pullup_from_supply(pos: Port[VoltageLink]) -> DigitalSource: return DigitalSource( - voltage_out=pos.link().voltage, + voltage=pos.link().voltage, output_thresholds=(-float("inf"), pos.link().voltage.lower()), high_driver=False, low_driver=False, @@ -472,7 +470,7 @@ def __init__(self) -> None: self.outer_port = self.Port( DigitalBidir( - voltage_out=RangeExpr(), + voltage=RangeExpr(), current_draw=RangeExpr(), voltage_limits=RangeExpr(), current_limits=RangeExpr(), @@ -658,7 +656,7 @@ def __call__( high_signal_driver: BoolLike = False, ) -> DigitalSource: return DigitalSource( - voltage_out=voltage_out, + voltage=voltage_out, output_thresholds=output_thresholds, pullup_capable=pullup_capable, pulldown_capable=pulldown_capable, diff --git a/edg/electronics_interfaces/DummyDevices.py b/edg/electronics_interfaces/DummyDevices.py index b4d91551f..c51ee5792 100644 --- a/edg/electronics_interfaces/DummyDevices.py +++ b/edg/electronics_interfaces/DummyDevices.py @@ -30,9 +30,10 @@ def __init__(self) -> None: class DummyDigitalSource(BaseDummyBlock[DigitalLink]): - def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL) -> None: + @deprecated_param_remap(("voltage_out", "voltage")) + def __init__(self, voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL) -> None: super().__init__() - self.io = self.Port(DigitalSource(voltage_out=voltage_out, current_limits=current_limits), [InOut]) + self.io = self.Port(DigitalSource(voltage=voltage, current_limits=current_limits), [InOut]) class DummyDigitalSink(BaseDummyBlock[DigitalLink]): @@ -52,9 +53,7 @@ def __init__( ) -> None: super().__init__() self.io = self.Port( - AnalogSource( - voltage=voltage, signal=signal, current_limits=current_limits, impedance=impedance - ), + AnalogSource(voltage=voltage, signal=signal, current_limits=current_limits, impedance=impedance), [InOut], ) @@ -83,7 +82,7 @@ def __init__(self, forced_current_draw: RangeLike) -> None: super().__init__() self.pwr_in = self.Port(VoltageSink(current_draw=forced_current_draw), [Input]) - self.pwr_out = self.Port(VoltageSource(voltage_out=self.pwr_in.link().voltage), [Output]) + self.pwr_out = self.Port(VoltageSource(voltage=self.pwr_in.link().voltage), [Output]) self.connect(self.pwr_in.net, self.pwr_out.net) @@ -96,7 +95,7 @@ def __init__(self, forced_current_limit: RangeLike) -> None: self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Input]) self.pwr_out = self.Port( - VoltageSource(voltage_out=self.pwr_in.link().voltage, current_limits=forced_current_limit), [Output] + VoltageSource(voltage=self.pwr_in.link().voltage, current_limits=forced_current_limit), [Output] ) self.connect(self.pwr_in.net, self.pwr_out.net) @@ -111,7 +110,7 @@ def __init__(self, forced_voltage: RangeLike) -> None: super().__init__() self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Input]) - self.pwr_out = self.Port(VoltageSource(voltage_out=forced_voltage), [Output]) + self.pwr_out = self.Port(VoltageSource(voltage=forced_voltage), [Output]) self.connect(self.pwr_in.net, self.pwr_out.net) self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw) @@ -124,7 +123,7 @@ def __init__(self, forced_voltage: RangeLike, forced_current: RangeLike) -> None super().__init__() self.pwr_in = self.Port(VoltageSink(current_draw=forced_current), [Input]) - self.pwr_out = self.Port(VoltageSource(voltage_out=forced_voltage), [Output]) + self.pwr_out = self.Port(VoltageSource(voltage=forced_voltage), [Output]) self.connect(self.pwr_in.net, self.pwr_out.net) @@ -165,7 +164,7 @@ def __init__(self, forced_current_draw: RangeLike = RangeExpr()) -> None: self.pwr_out = self.Port( DigitalSource( - voltage_out=self.pwr_in.link().voltage, + voltage=self.pwr_in.link().voltage, current_limits=RangeExpr.ALL, output_thresholds=self.pwr_in.link().output_thresholds, ), diff --git a/edg/electronics_interfaces/GroundPort.py b/edg/electronics_interfaces/GroundPort.py index f5f603a01..f30d59ef8 100644 --- a/edg/electronics_interfaces/GroundPort.py +++ b/edg/electronics_interfaces/GroundPort.py @@ -1,9 +1,12 @@ from __future__ import annotations from typing import TYPE_CHECKING, Any + +from deprecated import deprecated from typing_extensions import override from ..electronics_model import * +from ..util import deprecated_param_remap if TYPE_CHECKING: from .VoltagePorts import VoltageSource @@ -17,7 +20,7 @@ def _voltage_range(cls, port: Port[GroundLink]) -> RangeExpr: if isinstance(port, Ground): return port.is_connected().then_else(port.link().voltage, RangeExpr._to_expr_type(RangeExpr.ZERO)) elif isinstance(port, GroundReference): - return port.voltage_out + return port.voltage else: raise TypeError @@ -43,7 +46,7 @@ def contents(self) -> None: DescriptionString.FormatUnits(self.voltage_limits, "V"), ) - self.assign(self.voltage, self.ref.is_connected().then_else(self.ref.voltage_out, (0, 0) * Volt)) + self.assign(self.voltage, self.ref.is_connected().then_else(self.ref.voltage, (0, 0) * Volt)) self.assign(self.voltage_limits, self.gnds.intersection(lambda x: x.voltage_limits)) self.require(self.voltage_limits.contains(self.voltage), "overvoltage") @@ -53,14 +56,14 @@ def __init__(self) -> None: super().__init__() self.outer_port = self.Port(Ground()) - self.inner_link = self.Port(GroundReference(voltage_out=RangeExpr())) + self.inner_link = self.Port(GroundReference(voltage=RangeExpr())) @override def contents(self) -> None: super().contents() self.connect(self.outer_port.net, self.inner_link.net) - self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage) + self.assign(self.inner_link.voltage, self.outer_port.link().voltage) class GroundAdapterVoltageSource(PortAdapter["VoltageSource"]): @@ -69,7 +72,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Port(Ground()) - self.dst = self.Port(VoltageSource(voltage_out=self.src.link().voltage)) + self.dst = self.Port(VoltageSource(voltage=self.src.link().voltage)) self.connect(self.src.net, self.dst.net) @@ -81,7 +84,7 @@ def __init__(self) -> None: self.src = self.Port(Ground()) self.dst = self.Port( DigitalSource( - voltage_out=self.src.link().voltage, + voltage=self.src.link().voltage, output_thresholds=(self.src.link().voltage.lower(), FloatExpr._to_expr_type(float("inf"))), ) ) @@ -96,7 +99,7 @@ def __init__(self) -> None: self.src = self.Port(Ground()) self.dst = self.Port( AnalogSource( - voltage_out=self.src.link().voltage, + voltage=self.src.link().voltage, signal=self.src.link().voltage, ) ) @@ -130,13 +133,16 @@ def __init__(self, voltage_limits: RangeLike = Range.all()) -> None: class GroundReference(HasPassivePort, Port[GroundLink]): link_type = GroundLink - def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO) -> None: + @deprecated_param_remap(("voltage_out", "voltage")) + def __init__(self, voltage: RangeLike = RangeExpr.ZERO) -> None: super().__init__() self.net = self.Port(Passive()) - self.voltage_out = self.Parameter(RangeExpr(voltage_out)) + self.voltage = self.Parameter(RangeExpr(voltage)) - -from deprecated import deprecated + @property + @deprecated("use voltage") + def voltage_out(self) -> RangeExpr: + return self.voltage @deprecated("Use Ground() or GroundReference(...), Ground is no longer directioned") diff --git a/edg/electronics_interfaces/MergedBlocks.py b/edg/electronics_interfaces/MergedBlocks.py index b8a18d64e..a621694bd 100644 --- a/edg/electronics_interfaces/MergedBlocks.py +++ b/edg/electronics_interfaces/MergedBlocks.py @@ -13,7 +13,7 @@ def __init__(self) -> None: super().__init__() self.pwr_ins = self.Port(Vector(VoltageSink.empty())) - self.pwr_out = self.Port(VoltageSource(voltage_out=RangeExpr())) + self.pwr_out = self.Port(VoltageSource(voltage=RangeExpr())) self.generator_param(self.pwr_ins.requested()) @override @@ -24,7 +24,7 @@ def generate(self) -> None: elt_port = self.pwr_ins.append_elt(VoltageSink(current_draw=self.pwr_out.link().current_draw), in_request) self.connect(self.pwr_out.net, elt_port.net) - self.assign(self.pwr_out.voltage_out, self.pwr_ins.hull(lambda x: x.link().voltage)) + self.assign(self.pwr_out.voltage, self.pwr_ins.hull(lambda x: x.link().voltage)) def connected_from(self, *pwr_ins: Port[VoltageLink]) -> "MergedVoltageSource": for pwr_in in pwr_ins: @@ -39,7 +39,7 @@ def __init__(self) -> None: self.ins = self.Port(Vector(DigitalSink.empty())) self.out = self.Port( DigitalSource( - voltage_out=RangeExpr(), + voltage=RangeExpr(), output_thresholds=RangeExpr(), pullup_capable=BoolExpr(), pulldown_capable=BoolExpr(), @@ -55,7 +55,7 @@ def generate(self) -> None: elt_port = self.ins.append_elt(DigitalSink(current_draw=self.out.link().current_draw), in_request) self.connect(self.out.net, elt_port.net) - self.assign(self.out.voltage_out, self.ins.hull(lambda x: x.link().voltage)) + self.assign(self.out.voltage, self.ins.hull(lambda x: x.link().voltage)) self.assign(self.out.output_thresholds, self.ins.intersection(lambda x: x.link().output_thresholds)) self.assign(self.out.pullup_capable, self.ins.any(lambda x: x.link().pullup_capable)) self.assign(self.out.pulldown_capable, self.ins.any(lambda x: x.link().pulldown_capable)) @@ -77,7 +77,7 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]: def __init__(self) -> None: super().__init__() - self.output = self.Port(AnalogSource(voltage_out=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr())) + self.output = self.Port(AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr())) self.inputs = self.Port(Vector(AnalogSink.empty())) self.generator_param(self.inputs.requested()) @@ -92,7 +92,7 @@ def generate(self) -> None: ) self.connect(self.output.net, elt_port.net) - self.assign(self.output.voltage_out, self.inputs.hull(lambda x: x.link().voltage)) + self.assign(self.output.voltage, self.inputs.hull(lambda x: x.link().voltage)) self.assign(self.output.signal, self.inputs.hull(lambda x: x.link().signal)) self.assign( self.output.impedance, # covering cases of any or all sources driving diff --git a/edg/electronics_interfaces/VoltageDummy.py b/edg/electronics_interfaces/VoltageDummy.py index d7b8fbfb8..fef5c9bed 100644 --- a/edg/electronics_interfaces/VoltageDummy.py +++ b/edg/electronics_interfaces/VoltageDummy.py @@ -8,7 +8,7 @@ class DummyVoltageSource(BaseDummyBlock[VoltageLink]): def __init__( self, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, reverse_voltage_limits: RangeLike = RangeExpr.EMPTY, reverse_current_draw: RangeLike = RangeExpr.EMPTY, @@ -17,7 +17,7 @@ def __init__( self.io: VoltageSource = self.Port( VoltageSource( - voltage_out=voltage_out, + voltage=voltage, current_limits=current_limits, reverse_voltage_limits=reverse_voltage_limits, reverse_current_draw=reverse_current_draw, @@ -46,7 +46,7 @@ def __init__( self, voltage_limit: RangeLike = RangeExpr.ALL, current_draw: RangeLike = RangeExpr.ZERO, - reverse_voltage_out: RangeLike = RangeExpr.EMPTY, + reverse_voltage: RangeLike = RangeExpr.EMPTY, reverse_current_limits: RangeLike = RangeExpr.EMPTY, ) -> None: super().__init__() @@ -55,7 +55,7 @@ def __init__( VoltageSink( voltage_limits=voltage_limit, current_draw=current_draw, - reverse_voltage_out=reverse_voltage_out, + reverse_voltage=reverse_voltage, reverse_current_limits=reverse_current_limits, ), [Power, InOut], diff --git a/edg/electronics_interfaces/test_voltage_link.py b/edg/electronics_interfaces/test_voltage_link.py index 49581b70b..677abc859 100644 --- a/edg/electronics_interfaces/test_voltage_link.py +++ b/edg/electronics_interfaces/test_voltage_link.py @@ -9,7 +9,7 @@ class VoltageTestTop(DesignTop): def __init__(self) -> None: super().__init__() - self.src = self.Block(DummyVoltageSource(voltage_out=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) + self.src = self.Block(DummyVoltageSource(voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) self.sink = self.Block(DummyVoltageSink(voltage_limit=5 * Volt(tol=0.1), current_draw=1 * Amp(tol=0))) self.connect(self.src.io, self.sink.io) @@ -27,7 +27,7 @@ class OvervoltageTestTop(DesignTop): def __init__(self) -> None: super().__init__() - self.src = self.Block(DummyVoltageSource(voltage_out=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) + self.src = self.Block(DummyVoltageSource(voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) self.sink = self.Block(DummyVoltageSink(voltage_limit=3.3 * Volt(tol=0.1), current_draw=1 * Amp(tol=0))) self.connect(self.src.io, self.sink.io) @@ -37,7 +37,7 @@ class OvercurrentTestTop(DesignTop): def __init__(self) -> None: super().__init__() - self.src = self.Block(DummyVoltageSource(voltage_out=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) + self.src = self.Block(DummyVoltageSource(voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) self.sink1 = self.Block(DummyVoltageSink(voltage_limit=5 * Volt(tol=0.1), current_draw=1 * Amp(tol=0))) self.sink2 = self.Block(DummyVoltageSink(voltage_limit=5 * Volt(tol=0.1), current_draw=1 * Amp(tol=0))) self.connect(self.src.io, self.sink1.io, self.sink2.io) @@ -50,7 +50,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Block( DummyVoltageSource( - voltage_out=5 * Volt(tol=0), + voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp, reverse_voltage_limits=5 * Volt(tol=0.1), reverse_current_draw=0 * Amp(tol=0), @@ -60,7 +60,7 @@ def __init__(self) -> None: DummyVoltageSink( voltage_limit=5 * Volt(tol=0.1), current_draw=0 * Amp(tol=0), - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) @@ -81,7 +81,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Block( DummyVoltageSource( - voltage_out=5 * Volt(tol=0), + voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp, reverse_voltage_limits=5 * Volt(tol=0.1), reverse_current_draw=0 * Amp(tol=0), @@ -91,7 +91,7 @@ def __init__(self) -> None: DummyVoltageSink( voltage_limit=5 * Volt(tol=0.1), current_draw=0 * Amp(tol=0), - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) @@ -99,7 +99,7 @@ def __init__(self) -> None: DummyVoltageSink( voltage_limit=5 * Volt(tol=0.1), current_draw=0 * Amp(tol=0), - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) @@ -111,12 +111,12 @@ class ReverseNoSinkTest(DesignTop): def __init__(self) -> None: super().__init__() - self.src = self.Block(DummyVoltageSource(voltage_out=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) + self.src = self.Block(DummyVoltageSource(voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp)) self.sink = self.Block( DummyVoltageSink( voltage_limit=5 * Volt(tol=0.1), current_draw=0 * Amp(tol=0), - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) @@ -130,7 +130,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Block( DummyVoltageSource( - voltage_out=3.3 * Volt(tol=0), + voltage=3.3 * Volt(tol=0), current_limits=(0, 1) * Amp, reverse_voltage_limits=3.3 * Volt(tol=0.1), reverse_current_draw=0 * Amp(tol=0), @@ -140,7 +140,7 @@ def __init__(self) -> None: DummyVoltageSink( voltage_limit=(0, 14) * Volt, current_draw=0 * Amp(tol=0), - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) @@ -155,7 +155,7 @@ def __init__(self) -> None: super().__init__() self.src = self.Block( DummyVoltageSource( - voltage_out=5 * Volt(tol=0), + voltage=5 * Volt(tol=0), current_limits=(0, 1) * Amp, reverse_voltage_limits=(0, 14) * Volt, reverse_current_draw=0 * Amp(tol=0), @@ -165,7 +165,7 @@ def __init__(self) -> None: DummyVoltageSink( voltage_limit=5 * Volt(tol=0.1), current_draw=0 * Amp(tol=0), - reverse_voltage_out=12 * Volt(tol=0), + reverse_voltage=12 * Volt(tol=0), reverse_current_limits=(0, 1) * Amp, ) ) diff --git a/edg/electronics_model/PassivePort.py b/edg/electronics_model/PassivePort.py index ea9a179f7..142654319 100644 --- a/edg/electronics_model/PassivePort.py +++ b/edg/electronics_model/PassivePort.py @@ -74,7 +74,7 @@ def __init__( VoltageSink( voltage_limits=voltage_limits, current_draw=current_draw, - reverse_voltage_out=reverse_voltage, + reverse_voltage=reverse_voltage, reverse_current_limits=reverse_current_limits, ) ) @@ -147,7 +147,7 @@ def __init__( self, voltage_limits: RangeLike = RangeExpr.ALL, current_draw: RangeLike = RangeExpr.ZERO, - voltage_out: RangeLike = RangeExpr.ZERO, + voltage: RangeLike = RangeExpr.ZERO, current_limits: RangeLike = RangeExpr.ALL, input_thresholds: RangeLike = RangeExpr.EMPTY, output_thresholds: RangeLike = RangeExpr.ALL, @@ -164,7 +164,7 @@ def __init__( DigitalBidir( voltage_limits=voltage_limits, current_draw=current_draw, - voltage_out=voltage_out, + voltage=voltage, current_limits=current_limits, input_thresholds=input_thresholds, output_thresholds=output_thresholds, diff --git a/edg/parts/Jacdac.py b/edg/parts/Jacdac.py index c613d8471..196261869 100644 --- a/edg/parts/Jacdac.py +++ b/edg/parts/Jacdac.py @@ -70,7 +70,7 @@ def __init__(self, is_power_provider: BoolLike = False) -> None: # ports for power source mode self.gnd = self.Port(Ground(), [Common]) self.jd_pwr_src = self.Port( - VoltageSource(voltage_out=(3.5, 5.5) * Volt, current_limits=(0, 900) * mAmp), optional=True + VoltageSource(voltage=(3.5, 5.5) * Volt, current_limits=(0, 900) * mAmp), optional=True ) self.jd_pwr_sink = self.Port( @@ -86,7 +86,7 @@ def __init__(self, is_power_provider: BoolLike = False) -> None: self.jd_data = self.Port( DigitalBidir( voltage_limits=(0, 3.5) * Volt, - voltage_out=(0, 3.5) * Volt, + voltage=(0, 3.5) * Volt, input_thresholds=(0.3, 3.0) * Volt, output_thresholds=(0.3, 3.0) * Volt, ) @@ -209,7 +209,7 @@ def __init__(self) -> None: self.jd_data = self.Port( JacdacDataPort( DigitalBidir( - voltage_out=self.signal.link().voltage, + voltage=self.signal.link().voltage, voltage_limits=self.signal.link().voltage_limits, input_thresholds=self.signal.link().input_thresholds, output_thresholds=self.signal.link().output_thresholds, diff --git a/edg/parts/analog/CurrentSense_Ad8418.py b/edg/parts/analog/CurrentSense_Ad8418.py index 1cbe9cfdd..27522e131 100644 --- a/edg/parts/analog/CurrentSense_Ad8418.py +++ b/edg/parts/analog/CurrentSense_Ad8418.py @@ -30,7 +30,7 @@ def __init__(self, in_diff_range: RangeLike): self.in_diff_range = self.ArgParameter(in_diff_range) self.out = self.Port( AnalogSource( - voltage_out=(0.032, self.vs.link().voltage.upper() - 0.032), + voltage=(0.032, self.vs.link().voltage.upper() - 0.032), signal=(self.vref1.link().signal + self.vref2.link().signal) / 2 + (self.in_diff_range * self.GAIN), impedance=2 * Ohm(tol=0), # range not specified ) diff --git a/edg/parts/analog/adc/Mcp3561.py b/edg/parts/analog/adc/Mcp3561.py index f3d1d9cd3..7e7deb1a7 100644 --- a/edg/parts/analog/adc/Mcp3561.py +++ b/edg/parts/analog/adc/Mcp3561.py @@ -149,5 +149,5 @@ def generate(self) -> None: self.connect(self.vref, self.ic.vrefp) else: # dummy source, for the Vref capacitor (self.vrefp_source,), _ = self.chain( - self.Block(DummyVoltageSource(voltage_out=2.4 * Volt(tol=0.02))), self.ic.vrefp + self.Block(DummyVoltageSource(voltage=2.4 * Volt(tol=0.02))), self.ic.vrefp ) diff --git a/edg/parts/analog/opamp/Ina826.py b/edg/parts/analog/opamp/Ina826.py index 168a5f13c..e3872e904 100644 --- a/edg/parts/analog/opamp/Ina826.py +++ b/edg/parts/analog/opamp/Ina826.py @@ -138,4 +138,4 @@ def generate(self) -> None: self.forced = self.Block(ForcedAnalogSignal(self.ic.out.signal.intersect(output_diff_range))) self.connect(self.forced.signal_in, self.ic.out) - self.connect(self.forced.signal, self.output) + self.connect(self.forced.signal_out, self.output) diff --git a/edg/parts/connector/Connectors.py b/edg/parts/connector/Connectors.py index d97149533..875b377d5 100644 --- a/edg/parts/connector/Connectors.py +++ b/edg/parts/connector/Connectors.py @@ -5,16 +5,18 @@ from ...circuits import * from .Jst import JstShSmHorizontal +from ...util import deprecated_param_remap @abstract_block class PowerBarrelJack(Connector, PowerSource, Block): """Barrel jack that models a configurable voltage / max current power supply.""" - def __init__(self, voltage_out: RangeLike = RangeExpr(), current_limits: RangeLike = RangeExpr.ALL) -> None: + @deprecated_param_remap(("voltage_out", "voltage")) + def __init__(self, voltage: RangeLike = RangeExpr(), current_limits: RangeLike = RangeExpr.ALL) -> None: super().__init__() - self.pwr = self.Port(VoltageSource(voltage_out=voltage_out, current_limits=current_limits)) + self.pwr = self.Port(VoltageSource(voltage=voltage, current_limits=current_limits)) self.gnd = self.Port(Ground()) @@ -24,7 +26,7 @@ class Pj_102ah(PowerBarrelJack, FootprintBlock): @override def contents(self) -> None: super().contents() - self.require(self.pwr.voltage_out.within((0, 24) * Volt)) # datasheet ratings for connector + self.require(self.pwr.voltage.within((0, 24) * Volt)) # datasheet ratings for connector self.require(self.pwr.current_limits.within((0, 2.5) * Volt)) self.footprint( "J", @@ -46,7 +48,7 @@ class Pj_036ah(PowerBarrelJack, FootprintBlock): @override def contents(self) -> None: super().contents() - self.require(self.pwr.voltage_out.within((0, 24) * Volt)) # datasheet ratings for connector + self.require(self.pwr.voltage.within((0, 24) * Volt)) # datasheet ratings for connector self.require(self.pwr.current_limits.within((0, 5) * Volt)) self.footprint( @@ -85,7 +87,7 @@ def __init__( self.gnd.init_from(Ground()) self.pwr.init_from( VoltageSource( - voltage_out=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf + voltage=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf current_limits=(0, 5.5) * Amp, # arbitrary assuming low capacity, 10 C discharge reverse_voltage_limits=actual_voltage * RangeExpr._to_expr_type(charge_tolerance), reverse_current_draw=(0, 0) * Amp, diff --git a/edg/parts/connector/FanConnector.py b/edg/parts/connector/FanConnector.py index ddbd3d9ef..f2ba29321 100644 --- a/edg/parts/connector/FanConnector.py +++ b/edg/parts/connector/FanConnector.py @@ -29,7 +29,7 @@ def __init__(self) -> None: self.control = self.Port( DigitalBidir( voltage_limits=(0, 5.25) * Volt, - voltage_out=(0, 5.25) * Volt, + voltage=(0, 5.25) * Volt, pullup_capable=True, input_thresholds=(0.8, 0.8) * Volt, # only low threshold defined ) diff --git a/edg/parts/connector/UsbPorts.py b/edg/parts/connector/UsbPorts.py index 201aa5277..06180520b 100644 --- a/edg/parts/connector/UsbPorts.py +++ b/edg/parts/connector/UsbPorts.py @@ -1,6 +1,7 @@ from typing_extensions import override from ...circuits import * +from ...util import deprecated_param_remap from ...vendor_parts.jlc.JlcPart import JlcPart @@ -36,13 +37,14 @@ class UsbCReceptacle_Device(InternalSubcircuit, FootprintBlock, JlcPart): Pullup capable indicates whether this port (or more accurately, the device on the other side) can pull up the signal. In UFP (upstream-facing, device) mode the power source should pull up CC.""" + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, - voltage_out: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # allow custom PD voltage and current + voltage: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # allow custom PD voltage and current current_limits: RangeLike = UsbConnector.USB2_CURRENT_LIMITS, ) -> None: super().__init__() - self.pwr = self.Port(VoltageSource(voltage_out=voltage_out, current_limits=current_limits), optional=True) + self.pwr = self.Port(VoltageSource(voltage=voltage, current_limits=current_limits), optional=True) self.gnd = self.Port(Ground()) self.usb = self.Port(UsbHostPort(), optional=True) @@ -81,14 +83,15 @@ def contents(self) -> None: class UsbCReceptacle(UsbDeviceConnector, GeneratorBlock): """USB Type-C Receptacle that automatically generates the CC resistors if CC is not connected.""" + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, - voltage_out: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # allow custom PD voltage and current + voltage: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # allow custom PD voltage and current current_limits: RangeLike = UsbConnector.USB2_CURRENT_LIMITS, ) -> None: super().__init__() - self.conn = self.Block(UsbCReceptacle_Device(voltage_out=voltage_out, current_limits=current_limits)) + self.conn = self.Block(UsbCReceptacle_Device(voltage=voltage, current_limits=current_limits)) self.connect(self.pwr, self.conn.pwr) self.connect(self.gnd, self.conn.gnd) self.connect(self.usb, self.conn.usb) @@ -108,7 +111,7 @@ def generate(self) -> None: (self.cc_pull,), _ = self.chain(self.conn.cc, self.Block(UsbCcPulldownResistor())) self.connect(self.cc_pull.gnd, self.gnd) self.require( - self.pwr.voltage_out == UsbConnector.USB2_VOLTAGE_RANGE, + self.pwr.voltage == UsbConnector.USB2_VOLTAGE_RANGE, "when CC not connected, port restricted to USB 2.0 voltage", ) # note that the DFP (power source) can provide the max current, however the UFP (device) @@ -125,7 +128,7 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - self.pwr.init_from(VoltageSource(voltage_out=self.USB2_VOLTAGE_RANGE, current_limits=self.USB2_CURRENT_LIMITS)) + self.pwr.init_from(VoltageSource(voltage=self.USB2_VOLTAGE_RANGE, current_limits=self.USB2_CURRENT_LIMITS)) self.gnd.init_from(Ground()) self.usb.init_from(UsbHostPort()) @@ -149,7 +152,7 @@ def __init__(self) -> None: @override def contents(self) -> None: super().contents() - self.pwr.init_from(VoltageSource(voltage_out=self.USB2_VOLTAGE_RANGE, current_limits=self.USB2_CURRENT_LIMITS)) + self.pwr.init_from(VoltageSource(voltage=self.USB2_VOLTAGE_RANGE, current_limits=self.USB2_CURRENT_LIMITS)) self.gnd.init_from(Ground()) self.usb.init_from(UsbHostPort()) diff --git a/edg/parts/display/EInkBoostPowerPath.py b/edg/parts/display/EInkBoostPowerPath.py index 36c4c5636..f2fa4ec69 100644 --- a/edg/parts/display/EInkBoostPowerPath.py +++ b/edg/parts/display/EInkBoostPowerPath.py @@ -1,6 +1,7 @@ from typing_extensions import override from ...circuits import * +from ...util import deprecated_param_remap class EInkBoostPowerPath(Interface, KiCadSchematicBlock): @@ -8,9 +9,10 @@ class EInkBoostPowerPath(Interface, KiCadSchematicBlock): a bootstrap switched-cap circuit. Current is the peak current through the FET and diodes.""" + @deprecated_param_remap(("voltage_out", "voltage")) def __init__( self, - voltage_out: RangeLike, + voltage: RangeLike, current: RangeLike, inductance: RangeLike, in_capacitance: RangeLike, @@ -27,7 +29,7 @@ def __init__( self.gate = self.Port(DigitalSink.empty()) self.isense = self.Port(AnalogSource.empty(), optional=True) - self.voltage_out = self.ArgParameter(voltage_out) + self.voltage = self.ArgParameter(voltage) self.current = self.ArgParameter(current) self.inductance = self.ArgParameter(inductance) self.in_capacitance = self.ArgParameter(in_capacitance) @@ -41,7 +43,7 @@ def contents(self) -> None: self.fet = self.Block( Fet.NFet( - drain_voltage=self.voltage_out.hull((0, 0) * Volt), + drain_voltage=self.voltage.hull((0, 0) * Volt), drain_current=self.current, gate_voltage=self.gate.link().voltage, rds_on=(0, 400) * mOhm, @@ -52,7 +54,7 @@ def contents(self) -> None: self.in_cap = self.Block(DecouplingCapacitor(capacitance=self.in_capacitance)) diode_model = Diode( - reverse_voltage=self.voltage_out.hull((0, 0) * Volt), + reverse_voltage=self.voltage.hull((0, 0) * Volt), current=self.current.hull((0, 0) * Volt), voltage_drop=self.diode_voltage_drop, reverse_recovery_time=(0, 500e-9), # guess from Digikey's classification for "fast recovery" @@ -61,7 +63,7 @@ def contents(self) -> None: self.boot_neg_diode = self.Block(diode_model) self.boot_gnd_diode = self.Block(diode_model) - self.boot_cap = self.Block(Capacitor(capacitance=self.out_capacitance, voltage=self.voltage_out)) + self.boot_cap = self.Block(Capacitor(capacitance=self.out_capacitance, voltage=self.voltage)) out_cap_model = DecouplingCapacitor(capacitance=self.out_capacitance) self.out_cap = self.Block(out_cap_model) self.neg_out_cap = self.Block(out_cap_model) @@ -71,10 +73,10 @@ def contents(self) -> None: conversions={ "inductor.1": VoltageSink(), "diode.K": VoltageSource( - voltage_out=self.voltage_out, + voltage=self.voltage, ), "boot_neg_diode.A": VoltageSource( - voltage_out=-self.voltage_out, + voltage=-self.voltage, ), "boot_gnd_diode.K": Ground(), "sense.2": Ground(), diff --git a/edg/parts/display/EInk_Er_Epd027_2.py b/edg/parts/display/EInk_Er_Epd027_2.py index 8e6a160a3..7a63656af 100644 --- a/edg/parts/display/EInk_Er_Epd027_2.py +++ b/edg/parts/display/EInk_Er_Epd027_2.py @@ -39,14 +39,14 @@ def __init__(self) -> None: ) self.vdd1v8 = self.Port( VoltageSource( - voltage_out=1.8 * Volt(tol=0), # specs not given + voltage=1.8 * Volt(tol=0), # specs not given current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) self.vcom = self.Port( VoltageSource( - voltage_out=(2.4, 20) * Volt, # configurable up to VGH + voltage=(2.4, 20) * Volt, # configurable up to VGH current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) @@ -56,19 +56,19 @@ def __init__(self) -> None: # pin 4 is NC for this part self.vshr = self.Port( VoltageSource( - voltage_out=(0, 11) * Volt, # inferred from power selection register + voltage=(0, 11) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) self.vsh = self.Port( VoltageSource( - voltage_out=(2.4, 15) * Volt, # inferred from power selection register + voltage=(2.4, 15) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) self.vsl = self.Port( VoltageSource( - voltage_out=(-15, -2.4) * Volt, # inferred from power selection register + voltage=(-15, -2.4) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) diff --git a/edg/parts/display/Waveshare_Epd.py b/edg/parts/display/Waveshare_Epd.py index 0d0e870b5..4ccb548be 100644 --- a/edg/parts/display/Waveshare_Epd.py +++ b/edg/parts/display/Waveshare_Epd.py @@ -25,7 +25,7 @@ def __init__(self) -> None: ) self.vdd1v8 = self.Port( VoltageSource( - voltage_out=1.8 * Volt(tol=0), # specs not given + voltage=1.8 * Volt(tol=0), # specs not given current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) @@ -38,22 +38,22 @@ def __init__(self) -> None: self.vgl = self.Port( VoltageSource( - voltage_out=(-15, -2.5) * Volt, # inferred from power selection register + voltage=(-15, -2.5) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) self.vgh = self.Port( - VoltageSource(voltage_out=(2.5, 15) * Volt, current_limits=0 * mAmp(tol=0)) # only for external capacitor + VoltageSource(voltage=(2.5, 15) * Volt, current_limits=0 * mAmp(tol=0)) # only for external capacitor ) self.vsh = self.Port( VoltageSource( - voltage_out=(2.4, 15) * Volt, # inferred from power selection register + voltage=(2.4, 15) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) self.vsl = self.Port( VoltageSource( - voltage_out=(-15, -2.4) * Volt, # inferred from power selection register + voltage=(-15, -2.4) * Volt, # inferred from power selection register current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) @@ -63,7 +63,7 @@ def __init__(self) -> None: self.vcom = self.Port( VoltageSource( - voltage_out=(2.4, 20) * Volt, # configurable up to VGH + voltage=(2.4, 20) * Volt, # configurable up to VGH current_limits=0 * mAmp(tol=0), # only for external capacitor ) ) diff --git a/edg/parts/display/oled/Er_Oled_022.py b/edg/parts/display/oled/Er_Oled_022.py index 31bbdf9d6..c65d0c525 100644 --- a/edg/parts/display/oled/Er_Oled_022.py +++ b/edg/parts/display/oled/Er_Oled_022.py @@ -39,7 +39,7 @@ def __init__(self) -> None: self.iref = self.Port(AnalogSource.from_supply(self.vss, self.vdd)) self.vcomh = self.Port( VoltageSource( - voltage_out=self.vcc.link().voltage, current_limits=0 * mAmp(tol=0) # only for external capacitor + voltage=self.vcc.link().voltage, current_limits=0 * mAmp(tol=0) # only for external capacitor ) ) diff --git a/edg/parts/display/oled/Er_Oled_028.py b/edg/parts/display/oled/Er_Oled_028.py index d67e18140..0a550afd0 100644 --- a/edg/parts/display/oled/Er_Oled_028.py +++ b/edg/parts/display/oled/Er_Oled_028.py @@ -33,11 +33,11 @@ def __init__(self) -> None: ) self.vcomh = self.Port( VoltageSource( - voltage_out=self.vcc.link().voltage, current_limits=0 * mAmp(tol=0) # only for external capacitor + voltage=self.vcc.link().voltage, current_limits=0 * mAmp(tol=0) # only for external capacitor ) ) self.vdd = self.Port( - VoltageSource(voltage_out=(2.4, 2.6) * Volt, current_limits=0 * mAmp(tol=0)) # only for external capacitor + VoltageSource(voltage=(2.4, 2.6) * Volt, current_limits=0 * mAmp(tol=0)) # only for external capacitor ) self.vci = self.Port( VoltageSink(voltage_limits=(2.4, 3.5) * Volt, current_draw=(20, 300) * uAmp) # typ sleep to max operating diff --git a/edg/parts/display/oled/Er_Oled_091_3.py b/edg/parts/display/oled/Er_Oled_091_3.py index e6ee45c4a..c261c77c1 100644 --- a/edg/parts/display/oled/Er_Oled_091_3.py +++ b/edg/parts/display/oled/Er_Oled_091_3.py @@ -31,13 +31,13 @@ def __init__(self) -> None: self.vcc = self.Port( VoltageSource( - voltage_out=(6.4, 9) * Volt, + voltage=(6.4, 9) * Volt, current_limits=0 * mAmp(tol=0), # external draw not allowed, probably does 10-16mA ) ) self.vcomh = self.Port( VoltageSource( - voltage_out=self.vcc.voltage_out, # can program Vcomh to be fractions of Vcc + voltage=self.vcc.voltage, # can program Vcomh to be fractions of Vcc current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) diff --git a/edg/parts/display/oled/Er_Oled_096_1_1.py b/edg/parts/display/oled/Er_Oled_096_1_1.py index 9549ee89b..2bf39ed91 100644 --- a/edg/parts/display/oled/Er_Oled_096_1_1.py +++ b/edg/parts/display/oled/Er_Oled_096_1_1.py @@ -35,12 +35,12 @@ def __init__(self) -> None: current_draw=(1, 300) * uAmp, # sleep to operating ) ) - self.vcc = self.Port(VoltageSource(voltage_out=(7, 7.5) * Volt, current_limits=0 * mAmp(tol=0))) + self.vcc = self.Port(VoltageSource(voltage=(7, 7.5) * Volt, current_limits=0 * mAmp(tol=0))) self.iref = self.Port(AnalogSource.from_supply(self.vss, self.vdd)) self.vcomh = self.Port( VoltageSource( - voltage_out=self.vcc.voltage_out, # can program Vcomh to be fractions of Vcc + voltage=self.vcc.voltage, # can program Vcomh to be fractions of Vcc current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) diff --git a/edg/parts/display/oled/Er_Oled_096_1c.py b/edg/parts/display/oled/Er_Oled_096_1c.py index e0fa9b05e..e490ad4ca 100644 --- a/edg/parts/display/oled/Er_Oled_096_1c.py +++ b/edg/parts/display/oled/Er_Oled_096_1c.py @@ -44,14 +44,14 @@ def __init__(self) -> None: self.iref = self.Port(AnalogSource.from_supply(self.vss, self.vdd)) self.vcomh = self.Port( VoltageSource( - voltage_out=self.vcc.link().voltage * 0.86, # selectable up to 0.86 Vcc by command BEh + voltage=self.vcc.link().voltage * 0.86, # selectable up to 0.86 Vcc by command BEh current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) self.vsl = self.Port(Passive()) self.vp = self.Port( VoltageSource( - voltage_out=self.vcc.link().voltage * 0.5133, # selectable up to 0.5133 Vcc by command BBh + voltage=self.vcc.link().voltage * 0.5133, # selectable up to 0.5133 Vcc by command BBh current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) diff --git a/edg/parts/display/oled/test_oled_i2c_spi.py b/edg/parts/display/oled/test_oled_i2c_spi.py index 09b5cf791..3fa1192bd 100644 --- a/edg/parts/display/oled/test_oled_i2c_spi.py +++ b/edg/parts/display/oled/test_oled_i2c_spi.py @@ -11,7 +11,7 @@ class OledI2cTest(DesignTop): def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), @@ -40,7 +40,7 @@ def refinements(self) -> Refinements: class OledSpiTest(DesignTop): def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), diff --git a/edg/parts/human_interface/SpeakerDriver_Analog.py b/edg/parts/human_interface/SpeakerDriver_Analog.py index b31cc8ac0..f35d8c3df 100644 --- a/edg/parts/human_interface/SpeakerDriver_Analog.py +++ b/edg/parts/human_interface/SpeakerDriver_Analog.py @@ -25,7 +25,7 @@ def __init__(self) -> None: self.vo2 = self.Port(AnalogSource()) half_vdd = (self.pwr.link().voltage - self.gnd.link().voltage) / 2 + self.gnd.link().voltage - self.byp = self.Port(AnalogSource(voltage_out=half_vdd, signal=half_vdd)) + self.byp = self.Port(AnalogSource(voltage=half_vdd, signal=half_vdd)) @override def contents(self) -> None: diff --git a/edg/parts/interface/CanTransceiver_Iso1050.py b/edg/parts/interface/CanTransceiver_Iso1050.py index 2472617c0..8c852f8bd 100644 --- a/edg/parts/interface/CanTransceiver_Iso1050.py +++ b/edg/parts/interface/CanTransceiver_Iso1050.py @@ -16,7 +16,7 @@ def __init__(self) -> None: CanTransceiverPort( DigitalBidir( voltage_limits=(-0.5 * Volt, self.vcc1.link().voltage.lower() + 0.5 * Volt), - voltage_out=(0 * Volt, self.vcc1.link().voltage.lower()), + voltage=(0 * Volt, self.vcc1.link().voltage.lower()), current_limits=(-5, 5) * uAmp, input_thresholds=(0.8, 2) * Volt, output_thresholds=(0 * Volt, self.vcc1.link().voltage.lower()), diff --git a/edg/parts/interface/CanTransceiver_Sn65hvd230.py b/edg/parts/interface/CanTransceiver_Sn65hvd230.py index c5afb76c7..94d13c325 100644 --- a/edg/parts/interface/CanTransceiver_Sn65hvd230.py +++ b/edg/parts/interface/CanTransceiver_Sn65hvd230.py @@ -14,7 +14,7 @@ def __init__(self) -> None: CanTransceiverPort( DigitalBidir( voltage_limits=(-0.5 * Volt, self.vcc.link().voltage.lower() + 0.5 * Volt), - voltage_out=(0 * Volt, self.vcc.link().voltage.lower()), + voltage=(0 * Volt, self.vcc.link().voltage.lower()), current_limits=(-8, 8) * mAmp, # driver pin actually -40-48mA input_thresholds=(0.8, 2) * Volt, output_thresholds=(0 * Volt, self.vcc.link().voltage.lower()), diff --git a/edg/parts/interface/Rf_Pn7160.py b/edg/parts/interface/Rf_Pn7160.py index a6212c58b..7417ed2d8 100644 --- a/edg/parts/interface/Rf_Pn7160.py +++ b/edg/parts/interface/Rf_Pn7160.py @@ -267,19 +267,19 @@ def __init__(self) -> None: # internally generated supplies self.vdd = self.Port( VoltageSource( - voltage_out=(1.7, 1.95) * Volt, # Vddd pin characteristics + voltage=(1.7, 1.95) * Volt, # Vddd pin characteristics current_limits=(0, 0) * Amp, # connect decap only ) ) self.vddmid = self.Port( VoltageSource( - voltage_out=1.8 * Volt(tol=0), # assumed from external capacitor requirement + voltage=1.8 * Volt(tol=0), # assumed from external capacitor requirement current_limits=(0, 0) * Amp, # connect decap only ) ) self.vddtx = self.Port( VoltageSource( - voltage_out=(self.vddup.link().voltage - 0.3 * Volt).hull(2.5 * Volt), # up to 0.3v dropout + voltage=(self.vddup.link().voltage - 0.3 * Volt).hull(2.5 * Volt), # up to 0.3v dropout current_limits=(0, 0) * Amp, # connect decap only ) ) diff --git a/edg/parts/interface/Rf_Sx1262.py b/edg/parts/interface/Rf_Sx1262.py index 7be1c6ec4..becb0be2c 100644 --- a/edg/parts/interface/Rf_Sx1262.py +++ b/edg/parts/interface/Rf_Sx1262.py @@ -168,9 +168,7 @@ def __init__(self) -> None: ) # no separate current draw given, lumped w/ Vbat self.vreg = self.Port( - VoltageSource( # may be a LDO output or DC-DC input - voltage_out=1.55 * Volt(tol=0) # no tolerance specified - ) + VoltageSource(voltage=1.55 * Volt(tol=0)) # may be a LDO output or DC-DC input # no tolerance specified ) self.dcc_sw = self.Port(Passive()) @@ -179,7 +177,7 @@ def __init__(self) -> None: self.rfi_p = self.Port(Passive()) self.rfi_n = self.Port(Passive()) self.rfo = self.Port(Passive()) - self.vr_pa = self.Port(VoltageSource(voltage_out=(0, 3.1) * Volt)) # from power supply scheme figure + self.vr_pa = self.Port(VoltageSource(voltage=(0, 3.1) * Volt)) # from power supply scheme figure dio_model = DigitalBidir.from_supply( self.gnd, diff --git a/edg/parts/interface/UsbInterface_Ft232h.py b/edg/parts/interface/UsbInterface_Ft232h.py index 37438a7a5..e4e915f1c 100644 --- a/edg/parts/interface/UsbInterface_Ft232h.py +++ b/edg/parts/interface/UsbInterface_Ft232h.py @@ -17,19 +17,19 @@ def __init__(self) -> None: ) self.vccd = self.Port( VoltageSource( # is an output since VREGIN is +5v - voltage_out=(3.0, 3.6) * Volt, # not specified, inferred from limits of connected inputs + voltage=(3.0, 3.6) * Volt, # not specified, inferred from limits of connected inputs current_limits=(0, 62) * mAmp, # not specified, inferred from draw of connected inputs + EEPROM ) ) self.vcccore = self.Port( VoltageSource( # decouple with 0.1uF cap, recommended 1.62-1.98v - voltage_out=(1.62, 1.98) * Volt, # assumed from Vcore limits + voltage=(1.62, 1.98) * Volt, # assumed from Vcore limits current_limits=(0, 0) * mAmp, # not specified, external sourcing disallowed ) ) self.vcca = self.Port( VoltageSource( # 1.8v output, decouple with 0.1uF cap - voltage_out=(1.62, 1.98) * Volt, # assumed from Vcore limits + voltage=(1.62, 1.98) * Volt, # assumed from Vcore limits ) ) @@ -52,7 +52,7 @@ def __init__(self) -> None: ) self.osc = self.Port( - CrystalDriver(frequency_limits=12 * MHertz(tol=30e-6), voltage_out=self.vccd.link().voltage) + CrystalDriver(frequency_limits=12 * MHertz(tol=30e-6), voltage=self.vccd.link().voltage) ) # assumed self.ref = self.Port(AnalogSource.from_supply(self.gnd, self.vcca)) # assumed, connect 12k 1% resistor to GND self.usb = self.Port(UsbDevicePort()) diff --git a/edg/parts/interface/UsbPd_Fusb302b.py b/edg/parts/interface/UsbPd_Fusb302b.py index c5675369c..2f7403e46 100644 --- a/edg/parts/interface/UsbPd_Fusb302b.py +++ b/edg/parts/interface/UsbPd_Fusb302b.py @@ -18,7 +18,7 @@ def __init__(self) -> None: self.cc = self.Port(UsbCcPort()) i2c_model = DigitalBidir( # interestingly, IO maximum voltages are not specified - voltage_out=(0, 0.35) * Volt, # low-level output voltage + voltage=(0, 0.35) * Volt, # low-level output voltage current_limits=(-20, 0) * mAmp, # low-level output current limits input_thresholds=(0.51, 1.32) * Volt, output_thresholds=(0.35, float("inf")) * Volt, diff --git a/edg/parts/interface/UsbUart_Cp2102.py b/edg/parts/interface/UsbUart_Cp2102.py index d9ec6c712..8bfe2b78e 100644 --- a/edg/parts/interface/UsbUart_Cp2102.py +++ b/edg/parts/interface/UsbUart_Cp2102.py @@ -16,7 +16,7 @@ def __init__(self) -> None: ) self.vdd = self.Port( VoltageSource( # as input, limits are 3.0-3.6v - voltage_out=(3.0, 3.6) * Volt, # Table 6 + voltage=(3.0, 3.6) * Volt, # Table 6 current_limits=(0, 100) * mAmp, # Table 6 note ) ) diff --git a/edg/parts/microcontroller/Ch32v003.py b/edg/parts/microcontroller/Ch32v003.py index 44cf0a828..34c5f8b4c 100644 --- a/edg/parts/microcontroller/Ch32v003.py +++ b/edg/parts/microcontroller/Ch32v003.py @@ -109,7 +109,7 @@ def __init__(self, **kwargs: Any) -> None: ) # note, switched internal pull-up resistor, 35-55 kOhm self.osc = self.Port( - CrystalDriver(frequency_limits=(4, 25) * MHertz, voltage_out=self.vdd.link().voltage), optional=True + CrystalDriver(frequency_limits=(4, 25) * MHertz, voltage=self.vdd.link().voltage), optional=True ) # Table 3-10 crystal / resonator specs, typ 24 MHz self._dio_ft_model = DigitalBidir.from_supply( diff --git a/edg/parts/microcontroller/Ch32v203.py b/edg/parts/microcontroller/Ch32v203.py index a37041bf6..b770602ef 100644 --- a/edg/parts/microcontroller/Ch32v203.py +++ b/edg/parts/microcontroller/Ch32v203.py @@ -126,7 +126,7 @@ def __init__(self, **kwargs: Any) -> None: ) # note, switched internal pull-up resistor, 30-50 kOhm self.osc = self.Port( - CrystalDriver(frequency_limits=(3, 25) * MHertz, voltage_out=self.vdd.link().voltage), optional=True + CrystalDriver(frequency_limits=(3, 25) * MHertz, voltage=self.vdd.link().voltage), optional=True ) # Table 4-11 crystal / resonator specs, typ 8 MHz self._dio_ft_model = DigitalBidir.from_supply( diff --git a/edg/parts/microcontroller/Esp32.py b/edg/parts/microcontroller/Esp32.py index 518401468..7c69a8dc5 100644 --- a/edg/parts/microcontroller/Esp32.py +++ b/edg/parts/microcontroller/Esp32.py @@ -380,7 +380,7 @@ def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.vusb_out.init_from( - VoltageSource(voltage_out=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) + VoltageSource(voltage=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) ) self.generator_param( @@ -407,7 +407,7 @@ def generate(self) -> None: self.connect( self._generate_pwr_node( - voltage_out=3.3 * Volt(tol=0.05), + voltage=3.3 * Volt(tol=0.05), current_limits=UsbConnector.USB2_CURRENT_LIMITS, # tolerance is a guess ), self.model.pwr, diff --git a/edg/parts/microcontroller/Esp32c3.py b/edg/parts/microcontroller/Esp32c3.py index d74efa553..945d47347 100644 --- a/edg/parts/microcontroller/Esp32c3.py +++ b/edg/parts/microcontroller/Esp32c3.py @@ -96,7 +96,7 @@ def __init__(self, **kwargs: Any) -> None: # 10ppm requirement from ESP32-C3-WROOM schematic, and in ESP32 hardware design guidelines self.xtal = self.Port( # vdda domain assumed - CrystalDriver(frequency_limits=40 * MHertz(tol=10e-6), voltage_out=self.vdda.link().voltage), + CrystalDriver(frequency_limits=40 * MHertz(tol=10e-6), voltage=self.vdda.link().voltage), optional=self._model, ) @@ -542,7 +542,7 @@ def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.vusb_out.init_from( - VoltageSource(voltage_out=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) + VoltageSource(voltage=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) ) self.generator_param( @@ -572,7 +572,7 @@ def generate(self) -> None: ) self.connect( self._generate_pwr_node( - voltage_out=3.3 * Volt(tol=0.05), + voltage=3.3 * Volt(tol=0.05), current_limits=UsbConnector.USB2_CURRENT_LIMITS, # tolerance is a guess ), model_pwr, diff --git a/edg/parts/microcontroller/Esp32s3.py b/edg/parts/microcontroller/Esp32s3.py index 2ee8b29d3..da596dd94 100644 --- a/edg/parts/microcontroller/Esp32s3.py +++ b/edg/parts/microcontroller/Esp32s3.py @@ -358,7 +358,7 @@ def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.vusb_out.init_from( - VoltageSource(voltage_out=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) + VoltageSource(voltage=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) ) self.generator_param( @@ -385,7 +385,7 @@ def generate(self) -> None: self.connect( self._generate_pwr_node( - voltage_out=3.3 * Volt(tol=0.05), + voltage=3.3 * Volt(tol=0.05), current_limits=UsbConnector.USB2_CURRENT_LIMITS, # tolerance is a guess ), self.model.pwr, diff --git a/edg/parts/microcontroller/EspCommon.py b/edg/parts/microcontroller/EspCommon.py index 904b5a05c..52dffb07f 100644 --- a/edg/parts/microcontroller/EspCommon.py +++ b/edg/parts/microcontroller/EspCommon.py @@ -155,7 +155,7 @@ def contents(self) -> None: self.q_boot = self.Block(bjt_model) output_model = DigitalSource( - voltage_out=signal_voltage, + voltage=signal_voltage, current_limits=(0, 0) * Amp, # simplified for signal only output_thresholds=signal_thresholds, ) diff --git a/edg/parts/microcontroller/Lpc1549.py b/edg/parts/microcontroller/Lpc1549.py index 7c706b92c..5259e1dec 100644 --- a/edg/parts/microcontroller/Lpc1549.py +++ b/edg/parts/microcontroller/Lpc1549.py @@ -48,11 +48,11 @@ def __init__(self, **kwargs: Any) -> None: # Crystals from table 15, 32, 33 # TODO Table 32, model crystal load capacitance and series resistance ratings self.xtal = self.Port( - CrystalDriver(frequency_limits=(1, 25) * MHertz, voltage_out=self.pwr.link().voltage), optional=True + CrystalDriver(frequency_limits=(1, 25) * MHertz, voltage=self.pwr.link().voltage), optional=True ) # Assumed from "32kHz crystal" in 14.5 self.xtal_rtc = self.Port( - CrystalDriver(frequency_limits=(32, 33) * kHertz, voltage_out=self.pwr.link().voltage), optional=True + CrystalDriver(frequency_limits=(32, 33) * kHertz, voltage=self.pwr.link().voltage), optional=True ) self.swd = self.Port(SwdTargetPort.empty()) diff --git a/edg/parts/microcontroller/Rp2040.py b/edg/parts/microcontroller/Rp2040.py index 88cf58fae..599425734 100644 --- a/edg/parts/microcontroller/Rp2040.py +++ b/edg/parts/microcontroller/Rp2040.py @@ -76,7 +76,7 @@ def __init__(self, **kwargs: Any) -> None: ) self.vreg_vout = self.Port( VoltageSource( # actually adjustable, section 2.10.3 - voltage_out=1.1 * Volt(tol=0.03), # default is 1.1v nominal with 3% variation (Table 192) + voltage=1.1 * Volt(tol=0.03), # default is 1.1v nominal with 3% variation (Table 192) current_limits=(0, 100) * mAmp, # Table 1, max current ) ) @@ -120,7 +120,7 @@ def __init__(self, **kwargs: Any) -> None: self.xosc = self.Port( CrystalDriver( - frequency_limits=(1, 15) * MHertz, voltage_out=self.iovdd.link().voltage # datasheet 2.15.2.2 + frequency_limits=(1, 15) * MHertz, voltage=self.iovdd.link().voltage # datasheet 2.15.2.2 ), optional=True, ) @@ -464,7 +464,7 @@ def generate(self) -> None: ) ) self.vusb_out.init_from( - VoltageSource(voltage_out=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) + VoltageSource(voltage=UsbConnector.USB2_VOLTAGE_RANGE, current_limits=UsbConnector.USB2_CURRENT_LIMITS) ) self.model = self.Block( @@ -480,7 +480,7 @@ def generate(self) -> None: model_pwr = self.connect(self.model.iovdd, self.model.vreg_vin, self.model.adc_avdd, self.model.usb_vdd) self.connect( self._generate_pwr_node( - voltage_out=3.3 * Volt(tol=0.05), + voltage=3.3 * Volt(tol=0.05), current_limits=UsbConnector.USB2_CURRENT_LIMITS, # tolerance is a guess ), model_pwr, diff --git a/edg/parts/microcontroller/Stm32f103.py b/edg/parts/microcontroller/Stm32f103.py index 752b775fa..24a49f7ec 100644 --- a/edg/parts/microcontroller/Stm32f103.py +++ b/edg/parts/microcontroller/Stm32f103.py @@ -82,10 +82,10 @@ def __init__(self, **kwargs: Any) -> None: # TODO need to pass through to pin mapper # self.osc32 = self.Port(CrystalDriver(frequency_limits=32.768*kHertz(tol=0), # TODO actual tolerances - # voltage_out=self.pwr.link().voltage), + # voltage=self.pwr.link().voltage), # optional=True) # TODO other specs from Table 23 self.osc = self.Port( - CrystalDriver(frequency_limits=(4, 16) * MHertz, voltage_out=self.pwr.link().voltage), optional=True + CrystalDriver(frequency_limits=(4, 16) * MHertz, voltage=self.pwr.link().voltage), optional=True ) # Table 22 self.swd = self.Port(SwdTargetPort.empty()) diff --git a/edg/parts/microcontroller/Stm32f303.py b/edg/parts/microcontroller/Stm32f303.py index fde5e7fe9..9321d3a29 100644 --- a/edg/parts/microcontroller/Stm32f303.py +++ b/edg/parts/microcontroller/Stm32f303.py @@ -69,14 +69,14 @@ def __init__(self) -> None: self.vusb_out.init_from( VoltageSource( - voltage_out=(4.75 - 0.58, 5.1) + voltage=(4.75 - 0.58, 5.1) * Volt, # 4.75V USB - 0.58v BAT60JFILM drop to 5.1 from LD1117S50TR, ignoring ST890CDR current_limits=(0, 0.5) * Amp, # max USB draw # TODO higher from external power ) ) self.pwr_out.init_from( VoltageSource( - voltage_out=3.3 * Volt(tol=0.03), # LD39050PU33R worst-case Vout accuracy + voltage=3.3 * Volt(tol=0.03), # LD39050PU33R worst-case Vout accuracy current_limits=(0, 0.5) * Amp, # max USB current draw, LDO also guarantees 500mA output current ) ) diff --git a/edg/parts/microcontroller/nRF52840.py b/edg/parts/microcontroller/nRF52840.py index cabb9806a..4d3da872f 100644 --- a/edg/parts/microcontroller/nRF52840.py +++ b/edg/parts/microcontroller/nRF52840.py @@ -696,14 +696,14 @@ def generate(self) -> None: self.export_tap(self.gnd, self.device.gnd) self.connect( - self._generate_pwr_node(voltage_out=self._AP2112_3V3_OUT, current_limits=UsbConnector.USB2_CURRENT_LIMITS), + self._generate_pwr_node(voltage=self._AP2112_3V3_OUT, current_limits=UsbConnector.USB2_CURRENT_LIMITS), self.model.pwr, ) self.export_tap((self.pwr if self.get(self.pwr.is_connected()) else self.pwr_out).net, self.device.pwr) self.vusb_out.init_from( VoltageSource( - voltage_out=UsbConnector.USB2_VOLTAGE_RANGE - self._MBR120_DROP, + voltage=UsbConnector.USB2_VOLTAGE_RANGE - self._MBR120_DROP, current_limits=UsbConnector.USB2_CURRENT_LIMITS, ) ) diff --git a/edg/parts/microcontroller/test_mcu_wrapper.py b/edg/parts/microcontroller/test_mcu_wrapper.py index 4891d4d52..cb5c684d9 100644 --- a/edg/parts/microcontroller/test_mcu_wrapper.py +++ b/edg/parts/microcontroller/test_mcu_wrapper.py @@ -11,7 +11,7 @@ class OverallocateTest(DesignTop): def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), @@ -28,7 +28,7 @@ class FullMcuTest(DesignTop): # this uses all the pins, to catch potential automatic allocation errors def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), @@ -52,7 +52,7 @@ def __init__(self) -> None: class BaseMcuTest(DesignTop): def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), @@ -86,7 +86,7 @@ def refinements(self) -> Refinements: class AssignedI2cTest(DesignTop): def __init__(self) -> None: super().__init__() - self.pwr = self.Block(DummyVoltageSource(voltage_out=3.3 * Volt(tol=0))) + self.pwr = self.Block(DummyVoltageSource(voltage=3.3 * Volt(tol=0))) self.gnd = self.Block(DummyGround()) with self.implicit_connect( ImplicitConnect(self.pwr.io, [Power]), diff --git a/edg/parts/power/Batteries.py b/edg/parts/power/Batteries.py index 1a6584cd1..372344e80 100644 --- a/edg/parts/power/Batteries.py +++ b/edg/parts/power/Batteries.py @@ -16,7 +16,7 @@ def __init__( super().__init__(voltage, *args, **kwargs) self.pwr.init_from( VoltageSource( - voltage_out=self.gnd.link().voltage + voltage=self.gnd.link().voltage + actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf current_limits=(0, 10) * mAmp, ) @@ -52,7 +52,7 @@ def __init__( super().__init__(voltage, *args, **kwargs) self.pwr.init_from( VoltageSource( - voltage_out=self.gnd.link().voltage + actual_voltage, + voltage=self.gnd.link().voltage + actual_voltage, current_limits=(0, 2) * Amp, # arbitrary assuming low capacity, 1 C discharge ) ) @@ -90,7 +90,7 @@ def __init__( self.gnd.init_from(Ground()) self.pwr.init_from( VoltageSource( - voltage_out=self.gnd.link().voltage + actual_voltage, + voltage=self.gnd.link().voltage + actual_voltage, current_limits=(0, 1) * Amp, ) ) diff --git a/edg/parts/power/BatteryCharger_Mcp73831.py b/edg/parts/power/BatteryCharger_Mcp73831.py index 53af6cfce..168a11b59 100644 --- a/edg/parts/power/BatteryCharger_Mcp73831.py +++ b/edg/parts/power/BatteryCharger_Mcp73831.py @@ -23,7 +23,7 @@ def __init__(self, actual_charging_current: RangeLike) -> None: ) self.vbat = self.Port( VoltageSink( - reverse_voltage_out=(4.168, 4.232) * Volt, # -2 variant + reverse_voltage=(4.168, 4.232) * Volt, # -2 variant reverse_current_limits=self.actual_charging_current.hull(0 * Amp(tol=0)), ) ) diff --git a/edg/parts/power/LedDriver_Tps92200.py b/edg/parts/power/LedDriver_Tps92200.py index 5f0912bf1..84f727ad1 100644 --- a/edg/parts/power/LedDriver_Tps92200.py +++ b/edg/parts/power/LedDriver_Tps92200.py @@ -24,11 +24,11 @@ def __init__(self, peak_output_current: FloatLike): ) self.fb = self.Port(AnalogSink.from_supply(self.gnd, self.vin, voltage_limit_abs=(-0.1, 6) * Volt)) - self.sw = self.Port(VoltageSource(voltage_out=self.vin.link().voltage.hull(self.gnd.link().voltage))) + self.sw = self.Port(VoltageSource(voltage=self.vin.link().voltage.hull(self.gnd.link().voltage))) self.boot = self.Port( VoltageSink( voltage_limits=self.sw.link().voltage + (-0.1, 6) * Volt, - reverse_voltage_out=(4, 6) * Volt, # assumed from IN min to BOOT-SW abs max + reverse_voltage=(4, 6) * Volt, # assumed from IN min to BOOT-SW abs max reverse_current_limits=0 * Amp(tol=0), ) ) diff --git a/edg/parts/power/Ref30xx.py b/edg/parts/power/Ref30xx.py index a2f5783a0..bc23be102 100644 --- a/edg/parts/power/Ref30xx.py +++ b/edg/parts/power/Ref30xx.py @@ -35,7 +35,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, lcsc_part = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage) + self.assign(self.pwr_out.voltage, part_output_voltage) self.assign(self.lcsc_part, lcsc_part) self.assign(self.actual_basic_part, False) self.footprint( diff --git a/edg/parts/power/converter/AnalogDevices_Boost.py b/edg/parts/power/converter/AnalogDevices_Boost.py index 83b2878b3..6ef3b39da 100644 --- a/edg/parts/power/converter/AnalogDevices_Boost.py +++ b/edg/parts/power/converter/AnalogDevices_Boost.py @@ -17,7 +17,7 @@ def __init__(self, output_voltage: RangeLike): self.gnd = self.Port(Ground(), [Common]) self.sw = self.Port(VoltageSink()) self.fb = self.Port(AnalogSink(impedance=(8000, float("inf")) * kOhm)) - self.vout = self.Port(VoltageSource(voltage_out=output_voltage, current_limits=self.sw.link().current_limits)) + self.vout = self.Port(VoltageSource(voltage=output_voltage, current_limits=self.sw.link().current_limits)) self.nshdn = self.Port( DigitalSink( voltage_limits=(-0.3, 6) * Volt, current_draw=(0.01, 1) * uAmp, input_thresholds=(0.35, 1) * Volt @@ -58,7 +58,7 @@ def contents(self) -> None: super().contents() self.assign(self.actual_frequency, (380, 630) * kHertz) - self.require(self.pwr_out.voltage_out.within((2.2, 4.3) * Volt)) # >4.3v requires external diode + self.require(self.pwr_out.voltage.within((2.2, 4.3) * Volt)) # >4.3v requires external diode with self.implicit_connect( ImplicitConnect(self.pwr_in, [Power]), diff --git a/edg/parts/power/converter/CustomBuckBoost.py b/edg/parts/power/converter/CustomBuckBoost.py index a9e98eb0f..622e78f99 100644 --- a/edg/parts/power/converter/CustomBuckBoost.py +++ b/edg/parts/power/converter/CustomBuckBoost.py @@ -3,6 +3,7 @@ from typing_extensions import override from ....circuits import * +from ....util import deprecated_param_remap # These adapters are needed to properly orient the boost-side switch, since it outputs on the high side @@ -10,13 +11,14 @@ class VoltageSinkConnector(DummyDevice): """Connects two voltage sinks together (FET top sink to exterior source).""" - def __init__(self, voltage_out: RangeLike, a_current_limits: RangeLike, b_current_limits: RangeLike) -> None: + @deprecated_param_remap(("voltage_out", "voltage")) + def __init__(self, voltage: RangeLike, a_current_limits: RangeLike, b_current_limits: RangeLike) -> None: super().__init__() self.a = self.Port( - VoltageSource(voltage_out=voltage_out, current_limits=a_current_limits), [Input] + VoltageSource(voltage=voltage, current_limits=a_current_limits), [Input] ) # FET top: set output voltage, allow instantaneous current draw self.b = self.Port( - VoltageSource(voltage_out=voltage_out, current_limits=b_current_limits), [Output] + VoltageSource(voltage=voltage, current_limits=b_current_limits), [Output] ) # exterior source: set output voltage + Ilim self.connect(self.a.net, self.b.net) diff --git a/edg/parts/power/converter/DiodesInc_Boost.py b/edg/parts/power/converter/DiodesInc_Boost.py index 9efa8dee6..a7831c4b1 100644 --- a/edg/parts/power/converter/DiodesInc_Boost.py +++ b/edg/parts/power/converter/DiodesInc_Boost.py @@ -56,7 +56,7 @@ def contents(self) -> None: super().contents() self.assign(self.actual_frequency, (1.1, 1.9) * MHertz) - self.require(self.pwr_out.voltage_out.within((1.33, 29) * Volt)) + self.require(self.pwr_out.voltage.within((1.33, 29) * Volt)) with self.implicit_connect( ImplicitConnect(self.pwr_in, [Power]), @@ -90,7 +90,7 @@ def contents(self) -> None: self.rect = self.Block( Diode( - reverse_voltage=(0, self.pwr_out.voltage_out.upper()), + reverse_voltage=(0, self.pwr_out.voltage.upper()), current=self.pwr_out.link().current_draw, voltage_drop=(0, 0.4) * Volt, reverse_recovery_time=(0, 500) * nSecond, # guess from Digikey's classification for "fast recovery" @@ -101,7 +101,7 @@ def contents(self) -> None: self.pwr_out, self.rect.cathode.adapt_to( VoltageSource( - voltage_out=self.fb.actual_input_voltage, current_limits=self.power_path.switch.current_limits + voltage=self.fb.actual_input_voltage, current_limits=self.power_path.switch.current_limits ) ), ) diff --git a/edg/parts/power/converter/LinearRegulators.py b/edg/parts/power/converter/LinearRegulators.py index 9ee38587b..fcb77db5f 100644 --- a/edg/parts/power/converter/LinearRegulators.py +++ b/edg/parts/power/converter/LinearRegulators.py @@ -36,7 +36,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, lcsc_part = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage) + self.assign(self.pwr_out.voltage, part_output_voltage) self.assign(self.lcsc_part, lcsc_part) self.assign(self.actual_basic_part, False) self.footprint( @@ -99,7 +99,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage_nominal, part_number, jlc_number = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage_nominal * Volt(tol=TOLERANCE)) + self.assign(self.pwr_out.voltage, part_output_voltage_nominal * Volt(tol=TOLERANCE)) self.footprint( "U", "Package_TO_SOT_SMD:SOT-223-3_TabPin2", @@ -163,7 +163,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, jlc_number, jlc_basic_part = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage * Volt) + self.assign(self.pwr_out.voltage, part_output_voltage * Volt) self.footprint( "U", "Package_TO_SOT_SMD:SOT-223-3_TabPin2", @@ -242,7 +242,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage_nominal, part_number, jlc_number = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage_nominal * Volt(tol=TOLERANCE)) + self.assign(self.pwr_out.voltage, part_output_voltage_nominal * Volt(tol=TOLERANCE)) self.footprint( "U", "Package_TO_SOT_SMD:SOT-23-5", @@ -293,7 +293,7 @@ def __init__(self, output_voltage: RangeLike): self.assign(self.pwr_out.current_limits, (0, 0.6) * Amp) self.assign(self.actual_quiescent_current, (50, 80) * uAmp) self.assign(self.actual_dropout, (0, 0.25) * Volt) # worst-case @ 100mA Iout - self.assign(self.pwr_out.voltage_out, (3.234, 3.366) * Volt) + self.assign(self.pwr_out.voltage, (3.234, 3.366) * Volt) self.footprint( "U", "Package_TO_SOT_SMD:SOT-89-3", @@ -376,7 +376,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, part_dropout, part_max_current, lcsc_part, basic_part = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage * Volt) + self.assign(self.pwr_out.voltage, part_output_voltage * Volt) self.assign(self.actual_dropout, part_dropout * Volt) self.assign(self.pwr_out.current_limits, (0, part_max_current) * Amp) self.footprint( @@ -448,7 +448,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage_nominal, part_number, part_dropout, lcsc_part = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage_nominal * Volt(tol=TOLERANCE)) + self.assign(self.pwr_out.voltage, part_output_voltage_nominal * Volt(tol=TOLERANCE)) self.assign(self.actual_dropout, part_dropout * Volt) self.footprint( "U", @@ -526,7 +526,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage_nominal, part_number, jlc_number = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage_nominal * Volt(tol=TOLERANCE)) + self.assign(self.pwr_out.voltage, part_output_voltage_nominal * Volt(tol=TOLERANCE)) self.footprint( "U", "Package_TO_SOT_SMD:SOT-23-5", @@ -647,7 +647,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, footprint, jlc_number = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage) + self.assign(self.pwr_out.voltage, part_output_voltage) if footprint == "Package_TO_SOT_SMD:SOT-23-5": pinning: Mapping[str, HasPassivePort] = { "1": self.pwr_in, @@ -745,7 +745,7 @@ def generate(self) -> None: assert suitable_parts, "no regulator with compatible output" part_output_voltage, part_number, part_dropout, lcsc = suitable_parts[0] - self.assign(self.pwr_out.voltage_out, part_output_voltage) + self.assign(self.pwr_out.voltage, part_output_voltage) self.assign(self.actual_dropout, (0, part_dropout) * Volt) self.footprint( @@ -832,7 +832,7 @@ def generate(self) -> None: suitable_parts = [part for part in parts if part[0] in self.get(self.output_voltage)] assert suitable_parts, "no regulator with compatible output" - self.assign(self.pwr_out.voltage_out, suitable_parts[0][0]) + self.assign(self.pwr_out.voltage, suitable_parts[0][0]) self.assign(self.pwr_in.voltage_limits, suitable_parts[0][1]) self.assign(self.pwr_out.current_limits, (0, 100) * mAmp) self.assign(self.actual_quiescent_current, suitable_parts[0][2]) diff --git a/edg/parts/power/converter/Mp2722.py b/edg/parts/power/converter/Mp2722.py index baec464c2..3f0ed7677 100644 --- a/edg/parts/power/converter/Mp2722.py +++ b/edg/parts/power/converter/Mp2722.py @@ -19,21 +19,21 @@ def __init__(self, charging_current: RangeLike): ) self.sw = self.Port( VoltageSource( - voltage_out=self.vin.link().voltage.hull(self.gnd.link().voltage), current_limits=(0, 5) * Amp + voltage=self.vin.link().voltage.hull(self.gnd.link().voltage), current_limits=(0, 5) * Amp ) # up to 5A charge / system current ) # internal switch specs not defined, only bulk current limit defined self.assign(self.vin.current_draw, self.sw.link().current_draw) # TODO quiescent current self.pmid = self.Port( VoltageSource( - voltage_out=self.vin.link().voltage, # 5.08-5.22v in boost + voltage=self.vin.link().voltage, # 5.08-5.22v in boost current_limits=0 * Amp(tol=0), # decoupling only ) ) self.bst = self.Port( VoltageSink( voltage_limits=self.sw.link().voltage + (-0.3, 5) * Volt, - reverse_voltage_out=5 * Volt(tol=0), + reverse_voltage=5 * Volt(tol=0), reverse_current_limits=0 * Amp(tol=0), ) ) @@ -54,7 +54,7 @@ def __init__(self, charging_current: RangeLike): self.vcc = self.Port( VoltageSource( - voltage_out=3.65 * Volt(tol=0), # no tolerance given + voltage=3.65 * Volt(tol=0), # no tolerance given current_limits=(0, 5) * mAmp, # no limit given, can be used to drive stat LEDs ) ) @@ -65,7 +65,7 @@ def __init__(self, charging_current: RangeLike): ) self.rst = self.Port(dio_model, optional=True) # 200k internal pullup, float if unused self.int = self.Port(DigitalSource.low_from_supply(self.gnd), optional=True) - self.vrntc = self.Port(VoltageSource(voltage_out=self.vcc.voltage_out, current_limits=(0, 5) * mAmp)) + self.vrntc = self.Port(VoltageSource(voltage=self.vcc.voltage, current_limits=(0, 5) * mAmp)) self.ntc1 = self.Port(AnalogSink()) # required, doesn't seem to be any way to disable self.stat = self.Port(DigitalSource.low_from_supply(self.gnd), optional=True) # requires 10k pullup self.pg = self.Port(DigitalSource.low_from_supply(self.gnd), optional=True) # requires 10k pullup diff --git a/edg/parts/power/converter/TexasInstruments_Boost.py b/edg/parts/power/converter/TexasInstruments_Boost.py index 73882b0b2..6392b3dfb 100644 --- a/edg/parts/power/converter/TexasInstruments_Boost.py +++ b/edg/parts/power/converter/TexasInstruments_Boost.py @@ -145,7 +145,7 @@ def contents(self) -> None: self.connect( self.pwr_out, self.rect.cathode.adapt_to( - VoltageSource(voltage_out=self.fb.actual_input_voltage, current_limits=(0, max_current.upper())) + VoltageSource(voltage=self.fb.actual_input_voltage, current_limits=(0, max_current.upper())) ), ) @@ -270,7 +270,7 @@ def contents(self) -> None: self.rect = self.Block( Diode( - reverse_voltage=(0, self.pwr_out.voltage_out.upper()), + reverse_voltage=(0, self.pwr_out.voltage.upper()), current=self.pwr_out.link().current_draw, voltage_drop=(0, 0.8) * Volt, reverse_recovery_time=(0, 500) * nSecond, # guess from Digikey's classification for "fast recovery" @@ -281,11 +281,11 @@ def contents(self) -> None: self.pwr_out, self.rect.cathode.adapt_to( VoltageSource( - voltage_out=self.fb.actual_input_voltage, current_limits=self.power_path.switch.current_limits + voltage=self.fb.actual_input_voltage, current_limits=self.power_path.switch.current_limits ) ), ) self.require( - self.pwr_out.voltage_out.upper() + self.rect.actual_voltage_drop.upper() <= 40, "max SW voltage" + self.pwr_out.voltage.upper() + self.rect.actual_voltage_drop.upper() <= 40, "max SW voltage" ) diff --git a/edg/parts/power/converter/TexasInstruments_Buck.py b/edg/parts/power/converter/TexasInstruments_Buck.py index b1320dd6b..1ff425082 100644 --- a/edg/parts/power/converter/TexasInstruments_Buck.py +++ b/edg/parts/power/converter/TexasInstruments_Buck.py @@ -11,12 +11,12 @@ def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.pwr_in = self.Port(VoltageSink(voltage_limits=(4.5, 17) * Volt, current_draw=RangeExpr()), [Power]) - self.sw = self.Port(VoltageSource(voltage_out=self.pwr_in.link().voltage.hull(self.gnd.link().voltage))) + self.sw = self.Port(VoltageSource(voltage=self.pwr_in.link().voltage.hull(self.gnd.link().voltage))) self.fb = self.Port(AnalogSink(impedance=(8000, float("inf")) * kOhm)) # based on input current spec self.vbst = self.Port( VoltageSink( voltage_limits=(0, 23) * Volt, - reverse_voltage_out=(3.6, 6) * Volt, # assumed from UVLO to BST-SW abs max + reverse_voltage=(3.6, 6) * Volt, # assumed from UVLO to BST-SW abs max reverse_current_limits=0 * Amp(tol=0), ) ) @@ -112,7 +112,7 @@ def __init__(self) -> None: ) self.sw = self.Port( VoltageSource( - voltage_out=self.pwr_in.link().voltage.hull(self.gnd.link().voltage), + voltage=self.pwr_in.link().voltage.hull(self.gnd.link().voltage), current_limits=(0, 2) * Amp, # most conservative figures, low-side limited. TODO: better ones? ) ) # internal switch specs not defined, only bulk current limit defined @@ -122,7 +122,7 @@ def __init__(self) -> None: self.boot = self.Port( VoltageSink( voltage_limits=self.sw.link().voltage + (-0.3, 7) * Volt, - reverse_voltage_out=(4.5, 7) * Volt, # assumed from Vin,min to BST-SW abs max + reverse_voltage=(4.5, 7) * Volt, # assumed from Vin,min to BST-SW abs max reverse_current_limits=0 * Amp(tol=0), ) ) @@ -230,12 +230,12 @@ def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.vin = self.Port(VoltageSink(voltage_limits=(4.2, 80) * Volt, current_draw=RangeExpr()), [Power]) - self.sw = self.Port(VoltageSource(voltage_out=self.vin.link().voltage.hull(self.gnd.link().voltage))) + self.sw = self.Port(VoltageSource(voltage=self.vin.link().voltage.hull(self.gnd.link().voltage))) self.fb = self.Port(AnalogSink(impedance=(10, float("inf")) * MOhm)) # assumed given RFbb maximum spec self.boot = self.Port( VoltageSink( voltage_limits=self.sw.link().voltage + (-0.3, 5.5) * Volt, - reverse_voltage_out=(3.8, 5.5) * Volt, # assumed from UVLO to BOOT-SW abs max + reverse_voltage=(3.8, 5.5) * Volt, # assumed from UVLO to BOOT-SW abs max reverse_current_limits=0 * Amp(tol=0), ) ) diff --git a/edg/parts/power/converter/TexasInstruments_SwitchedCap.py b/edg/parts/power/converter/TexasInstruments_SwitchedCap.py index b6bc2f632..bf917cf87 100644 --- a/edg/parts/power/converter/TexasInstruments_SwitchedCap.py +++ b/edg/parts/power/converter/TexasInstruments_SwitchedCap.py @@ -15,7 +15,7 @@ def __init__(self) -> None: self.capn = self.Port(Passive()) self.capp = self.Port(Passive()) - self.out = self.Port(VoltageSource(voltage_out=-self.vp.link().voltage, current_limits=(0, 40) * mAmp)) + self.out = self.Port(VoltageSource(voltage=-self.vp.link().voltage, current_limits=(0, 40) * mAmp)) self.assign(self.vp.current_draw, (1, 500) * uAmp + self.out.link().current_draw) # self.sd = self.Port(DigitalSink.from_supply( @@ -72,7 +72,7 @@ def contents(self) -> None: 2 / self.ic.FREQUENCY.lower / (self.output_resistance_limit - 2 * self.ic.SWITCH_RESISTANCE.upper), float("inf"), ), - voltage=self.pwr_out.voltage_out, + voltage=self.pwr_out.voltage, ) ) self.connect(self.cf.neg, self.ic.capn) diff --git a/edg/parts/power/converter/Torex_Boost.py b/edg/parts/power/converter/Torex_Boost.py index 20ff6fbe8..69cbd4913 100644 --- a/edg/parts/power/converter/Torex_Boost.py +++ b/edg/parts/power/converter/Torex_Boost.py @@ -65,7 +65,7 @@ def generate(self) -> None: self.assign(self.actual_frequency, part_frequency) self.assign(self.actual_current_limit, (0, part_current.lower)) - self.vout.init_from(VoltageSource(voltage_out=part_voltage, current_limits=self.sw.link().current_limits)) + self.vout.init_from(VoltageSource(voltage=part_voltage, current_limits=self.sw.link().current_limits)) self.footprint( "U", @@ -105,7 +105,7 @@ def contents(self) -> None: self.power_path = imp.Block( BoostConverterPowerPath( self.pwr_in.link().voltage, - self.ic.vout.voltage_out, + self.ic.vout.voltage, self.actual_frequency, self.pwr_out.link().current_draw, self.ic.actual_current_limit, diff --git a/edg/parts/power/gate_driver/Ncp3420.py b/edg/parts/power/gate_driver/Ncp3420.py index a0ddba49a..23aa6dafd 100644 --- a/edg/parts/power/gate_driver/Ncp3420.py +++ b/edg/parts/power/gate_driver/Ncp3420.py @@ -115,7 +115,7 @@ def generate(self) -> None: ) self.connect( self.boot.cathode.adapt_to( - VoltageSource(voltage_out=self.high_gnd.link().voltage + self.pwr.link().voltage) + VoltageSource(voltage=self.high_gnd.link().voltage + self.pwr.link().voltage) ), self.ic.bst, ) diff --git a/edg/parts/power/gate_driver/Ucc27282.py b/edg/parts/power/gate_driver/Ucc27282.py index 0e75bde07..d058e8e55 100644 --- a/edg/parts/power/gate_driver/Ucc27282.py +++ b/edg/parts/power/gate_driver/Ucc27282.py @@ -31,7 +31,7 @@ def __init__(self) -> None: ) self.hb = self.Port( VoltageSource( - voltage_out=self.hs.link().voltage + self.vdd.link().voltage, + voltage=self.hs.link().voltage + self.vdd.link().voltage, ) ) self.ho = self.Port( diff --git a/edg/parts/power/motor/Bldc_Drv8313.py b/edg/parts/power/motor/Bldc_Drv8313.py index 0ab90662c..56e10c8d4 100644 --- a/edg/parts/power/motor/Bldc_Drv8313.py +++ b/edg/parts/power/motor/Bldc_Drv8313.py @@ -19,13 +19,13 @@ def __init__(self) -> None: ) self.v3p3 = self.Port( VoltageSource( # internal regulator, bypass with 6.3v, 0.47uF capacitor - voltage_out=(3.1, 3.52) * Volt, # Table 6.5 V3P3 voltage + voltage=(3.1, 3.52) * Volt, # Table 6.5 V3P3 voltage current_limits=(0, 10) * mAmp, # Table 6.3 max V3P3 load current ) ) self.vcp = self.Port( VoltageSource( - voltage_out=self.vm.link().voltage + 12 * Volt(tol=0.2), # assumed, from Vcp abs max ratings + voltage=self.vm.link().voltage + 12 * Volt(tol=0.2), # assumed, from Vcp abs max ratings current_limits=0 * Amp(tol=0), ) ) # charge pump, 16V 0.1uF capacitor to Vm diff --git a/edg/parts/power/motor/MotorDriver_Drv8833.py b/edg/parts/power/motor/MotorDriver_Drv8833.py index 909570132..95f5005f1 100644 --- a/edg/parts/power/motor/MotorDriver_Drv8833.py +++ b/edg/parts/power/motor/MotorDriver_Drv8833.py @@ -11,13 +11,13 @@ def __init__(self) -> None: self.gnd = self.Port(Ground()) self.vint = self.Port( VoltageSource( # internal supply bypass - voltage_out=(0, 6.3) * Volt, # inferred from capacitor rating, actual voltage likely lower + voltage=(0, 6.3) * Volt, # inferred from capacitor rating, actual voltage likely lower current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) self.vcp = self.Port( VoltageSource( # assumed charge pump is 2x Vm - voltage_out=(self.vm.link().voltage - self.gnd.link().voltage) * 2 + self.gnd.link().voltage, + voltage=(self.vm.link().voltage - self.gnd.link().voltage) * 2 + self.gnd.link().voltage, current_limits=0 * mAmp(tol=0), # external draw not allowed ) ) diff --git a/edg/parts/power/motor/StepperDriver_A4988.py b/edg/parts/power/motor/StepperDriver_A4988.py index bb69a3da3..2c66f7f1c 100644 --- a/edg/parts/power/motor/StepperDriver_A4988.py +++ b/edg/parts/power/motor/StepperDriver_A4988.py @@ -18,13 +18,13 @@ def __init__(self) -> None: self.vdd = self.Port(VoltageSink(voltage_limits=(3, 5.5) * Volt, current_draw=(0.010, 8) * mAmp)) self.vreg = self.Port( VoltageSource( - voltage_out=(7, 7) * Volt, # "nominal output voltage" + voltage=(7, 7) * Volt, # "nominal output voltage" current_limits=0 * Amp(tol=0), # regulator decoupling terminal only ) ) self.vcp = self.Port( VoltageSource( # assumed this doubles vbb (worst case), arbitrarily connected to vbb1 - voltage_out=self.vbb1.link().voltage * 2 - self.gnd.link().voltage, current_limits=0 * Amp(tol=0) + voltage=self.vbb1.link().voltage * 2 - self.gnd.link().voltage, current_limits=0 * Amp(tol=0) ) ) self.cp1 = self.Port(Passive()) diff --git a/edg/parts/sensor/Mag_Qmc5883.py b/edg/parts/sensor/Mag_Qmc5883.py index 8bf809f03..b898c84e9 100644 --- a/edg/parts/sensor/Mag_Qmc5883.py +++ b/edg/parts/sensor/Mag_Qmc5883.py @@ -27,7 +27,7 @@ def __init__(self) -> None: self.setp = self.Port(Passive()) self.setc = self.Port(Passive()) - self.c1 = self.Port(VoltageSource(voltage_out=self.vdd.link().voltage, current_limits=(0, 0) * Amp)) # assumed + self.c1 = self.Port(VoltageSource(voltage=self.vdd.link().voltage, current_limits=(0, 0) * Amp)) # assumed @override def contents(self) -> None: @@ -107,7 +107,7 @@ def __init__(self) -> None: input_threshold_factor=(0.3, 0.7), ) self.i2c = self.Port(I2cTarget(dio_model)) - self.c1 = self.Port(VoltageSource(voltage_out=self.vdd.link().voltage, current_limits=(0, 0) * Amp)) # assumed + self.c1 = self.Port(VoltageSource(voltage=self.vdd.link().voltage, current_limits=(0, 0) * Amp)) # assumed @override def contents(self) -> None: diff --git a/edg/parts/sensor/Rtc_Pcf2129.py b/edg/parts/sensor/Rtc_Pcf2129.py index d86a40e37..54128a397 100644 --- a/edg/parts/sensor/Rtc_Pcf2129.py +++ b/edg/parts/sensor/Rtc_Pcf2129.py @@ -15,7 +15,7 @@ def __init__(self) -> None: dio_model = DigitalBidir( voltage_limits=(-0.5, self.pwr.link().voltage.lower() + 0.5), - voltage_out=(0, self.pwr.link().voltage.lower()), + voltage=(0, self.pwr.link().voltage.lower()), current_limits=(-1, 1) * mAmp, # TODO higher sink current on SDA/nCE input_thresholds=(0.25 * self.pwr.link().voltage.upper(), 0.7 * self.pwr.link().voltage.upper()), output_thresholds=(0, self.pwr.link().voltage.upper()), @@ -28,7 +28,7 @@ def __init__(self) -> None: self.clkout = self.Port(opendrain_model, optional=True) self.int = self.Port(opendrain_model, optional=True) - self.bbs = self.Port(VoltageSource(voltage_out=self.pwr_bat.link().voltage)) + self.bbs = self.Port(VoltageSource(voltage=self.pwr_bat.link().voltage)) @override def contents(self) -> None: diff --git a/edg/util/__init__.py b/edg/util/__init__.py index cdb6e0d5d..0ea9d05eb 100644 --- a/edg/util/__init__.py +++ b/edg/util/__init__.py @@ -15,7 +15,7 @@ def deprecated_param_remap(*params: Tuple[str, str]) -> Callable[[Callable[P, R] def decorator(func: Callable[P, R]) -> Callable[P, R]: @wraps(func) - def wrapper(self, *args: Any, **kwargs: Any) -> R: + def wrapper(self: Any, *args: Any, **kwargs: Any) -> R: for old_param, new_param in params: if old_param in kwargs: warnings.warn( @@ -27,6 +27,6 @@ def wrapper(self, *args: Any, **kwargs: Any) -> R: kwargs[new_param] = kwargs.pop(old_param) return func(self, *args, **kwargs) - return wrapper + return wrapper # type: ignore return decorator diff --git a/examples/test_can_adapter.py b/examples/test_can_adapter.py index 8f71f9e82..831807299 100644 --- a/examples/test_can_adapter.py +++ b/examples/test_can_adapter.py @@ -12,7 +12,7 @@ class Obd2Connector(FootprintBlock): def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) - self.pwr = self.Port(VoltageSource(voltage_out=(10, 25) * Volt)) + self.pwr = self.Port(VoltageSource(voltage=(10, 25) * Volt)) self.can = self.Port(CanDiffPort()) diff --git a/examples/test_datalogger.py b/examples/test_datalogger.py index e015b27b3..9e95c42bd 100644 --- a/examples/test_datalogger.py +++ b/examples/test_datalogger.py @@ -89,7 +89,7 @@ def __init__(self, charging_current: RangeLike, sense_resistance: RangeLike, vol ) self.connect( self.diode.anode.adapt_to(VoltageSink()), - self.fet.drain.adapt_to(VoltageSource(voltage_out=self.pwr.link().voltage)), + self.fet.drain.adapt_to(VoltageSource(voltage=self.pwr.link().voltage)), self.sc_out, ) @@ -97,7 +97,7 @@ def __init__(self, charging_current: RangeLike, sense_resistance: RangeLike, vol self.pwr, self.diode.cathode.adapt_to( VoltageSource( - voltage_out=( + voltage=( self.pwr.link().voltage.lower() - self.voltage_drop.upper(), self.pwr.link().voltage.upper(), ) @@ -122,7 +122,7 @@ def __init__(self, charging_current: RangeLike, sense_resistance: RangeLike, vol self.amp.inn, self.sense.b.adapt_to( AnalogSource( - voltage_out=(0, self.pwr.link().voltage.upper()), + voltage=(0, self.pwr.link().voltage.upper()), # TODO calculate operating signal level ) ), diff --git a/examples/test_deskcontroller.py b/examples/test_deskcontroller.py index fe9c49daa..328638817 100644 --- a/examples/test_deskcontroller.py +++ b/examples/test_deskcontroller.py @@ -14,7 +14,7 @@ def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.pwr = self.Port( - VoltageSource(voltage_out=5 * Volt(tol=0), current_limits=(0, 300) * mAmp) + VoltageSource(voltage=5 * Volt(tol=0), current_limits=(0, 300) * mAmp) ) # reportedly drives at least 300mA self.uart = self.Port(UartPort(DigitalBidir.from_supply(self.gnd, self.pwr))) diff --git a/examples/test_fcml.py b/examples/test_fcml.py index be69f8e98..b059721b1 100644 --- a/examples/test_fcml.py +++ b/examples/test_fcml.py @@ -35,7 +35,7 @@ def __init__(self, reverse_voltage: RangeLike, current: RangeLike, voltage_drop: [Power, Input], ) self.pwr_out = self.Port( - VoltageSource(voltage_out=self.pwr_in.link().voltage, current_limits=Range.all()), [Output] + VoltageSource(voltage=self.pwr_in.link().voltage, current_limits=Range.all()), [Output] ) # ignore voltage drop self.diode = self.Block(Diode(reverse_voltage=reverse_voltage, current=current, voltage_drop=voltage_drop)) @@ -168,9 +168,9 @@ def generate(self) -> None: }, conversions={ "low_in": Ground(), # TODO better conventions for Ground vs VoltageSink|Source - "low_out": VoltageSource(voltage_out=self.low_in.link().voltage), + "low_out": VoltageSource(voltage=self.low_in.link().voltage), "high_in": VoltageSink(current_draw=self.high_out.link().current_draw), - "high_out": VoltageSource(voltage_out=self.low_in.link().voltage), + "high_out": VoltageSource(voltage=self.low_in.link().voltage), "low_boot_cap.1": VoltageSink(), "high_boot_cap.1": VoltageSink(), "low_gate": DigitalSink(), # TODO model gate current draw @@ -281,7 +281,7 @@ def generate(self) -> None: self.pwr_out, self.inductor.b.adapt_to( VoltageSource( - voltage_out=self.output_voltage, + voltage=self.output_voltage, current_limits=BuckConverterPowerPath._ilim_expr( self.inductor.actual_current_rating, self.sw_current_limits, self.actual_inductor_current_ripple ), diff --git a/examples/test_high_switch.py b/examples/test_high_switch.py index dafa5e9a0..ba2eb9dd1 100644 --- a/examples/test_high_switch.py +++ b/examples/test_high_switch.py @@ -84,7 +84,7 @@ def __init__(self) -> None: self.pwr = self.Port( VoltageSource( - voltage_out=12 * Volt(tol=0.1), current_limits=(0, 3) * Amp # TODO get actual limits from LVPDB? + voltage=12 * Volt(tol=0.1), current_limits=(0, 3) * Amp # TODO get actual limits from LVPDB? ) ) self.gnd = self.Port(Ground()) @@ -112,7 +112,7 @@ def __init__(self) -> None: self.pwr = self.Port( VoltageSource( - voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick? + voltage=(7, 14) * Volt, # TODO get limits from CAN power brick? current_limits=(0, 0.15) * Amp, # TODO get actual limits from ??? ) ) @@ -144,7 +144,7 @@ def __init__(self) -> None: self.pwr = self.Port( VoltageSource( - voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick? + voltage=(7, 14) * Volt, # TODO get limits from CAN power brick? current_limits=(0, 0.15) * Amp, # TODO get actual limits from ??? ) ) @@ -176,7 +176,7 @@ def __init__(self) -> None: self.pwr = self.Port( VoltageSource( - voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick? + voltage=(7, 14) * Volt, # TODO get limits from CAN power brick? current_limits=(0, 0.15) * Amp, # TODO get actual limits from ??? ) ) diff --git a/examples/test_iot_blinds.py b/examples/test_iot_blinds.py index 1fb8ffc7e..7e31a8338 100644 --- a/examples/test_iot_blinds.py +++ b/examples/test_iot_blinds.py @@ -34,7 +34,7 @@ class PowerInConnector(Connector): def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) - self.pwr = self.Port(VoltageSource(voltage_out=(10, 25) * Volt, current_limits=(0, 1) * Amp)) + self.pwr = self.Port(VoltageSource(voltage=(10, 25) * Volt, current_limits=(0, 1) * Amp)) self.conn = self.Block(JstPh()).connected({"1": self.gnd, "2": self.pwr}) diff --git a/examples/test_iot_display.py b/examples/test_iot_display.py index cd0ccd2d0..420bfed47 100644 --- a/examples/test_iot_display.py +++ b/examples/test_iot_display.py @@ -17,7 +17,7 @@ def __init__(self, frequency: RangeLike = RangeExpr.ZERO, max_rds: FloatLike = 1 self.pwr = self.Port(VoltageSink(current_draw=RangeExpr()), [Power]) self.output = self.Port( - VoltageSource(voltage_out=self.pwr.link().voltage, current_limits=RangeExpr()), + VoltageSource(voltage=self.pwr.link().voltage, current_limits=RangeExpr()), [Output], ) self.control = self.Port(DigitalSink(), [Input]) diff --git a/examples/test_iot_fan.py b/examples/test_iot_fan.py index 60bab7ef6..51f59dc33 100644 --- a/examples/test_iot_fan.py +++ b/examples/test_iot_fan.py @@ -117,8 +117,8 @@ def contents(self) -> None: super().contents() # only populate ONE of these - self.pwr = self.Block(PowerBarrelJack(voltage_out=(10, 24) * Volt, current_limits=(0, 5) * Amp)) - self.usb = self.Block(UsbCReceptacle(voltage_out=(5, 20) * Volt, current_limits=(0, 5) * Amp)) + self.pwr = self.Block(PowerBarrelJack(voltage=(10, 24) * Volt, current_limits=(0, 5) * Amp)) + self.usb = self.Block(UsbCReceptacle(voltage=(5, 20) * Volt, current_limits=(0, 5) * Amp)) self.pwr_merge = self.Block(MergedVoltageSource()).connected_from(self.pwr.pwr, self.usb.pwr) self.gnd = self.connect(self.pwr.gnd, self.usb.gnd) diff --git a/examples/test_iot_iron.py b/examples/test_iot_iron.py index f2e0e40bc..26aa3e978 100644 --- a/examples/test_iot_iron.py +++ b/examples/test_iot_iron.py @@ -21,7 +21,7 @@ def __init__( self.pwr = self.Port(VoltageSink(current_draw=current_draw)) self.thermocouple = self.Port( AnalogSource( - voltage_out=self.gnd.link().voltage + (0, 14.3) * mVolt, + voltage=self.gnd.link().voltage + (0, 14.3) * mVolt, signal=self.gnd.link().voltage + (0, 14.3) * mVolt, # up to ~350 C ), optional=True, @@ -50,7 +50,7 @@ def contents(self) -> None: super().contents() # assume minimum power input of 12v from PD, you probably don't want a 5v USB 15W soldering iron - self.usb = self.Block(UsbCReceptacle(voltage_out=(12, 20) * Volt, current_limits=(0, 5) * Amp)) + self.usb = self.Block(UsbCReceptacle(voltage=(12, 20) * Volt, current_limits=(0, 5) * Amp)) self.vusb = self.connect(self.usb.pwr) self.gnd = self.connect(self.usb.gnd) diff --git a/examples/test_iot_led_driver.py b/examples/test_iot_led_driver.py index c624726c2..97d6f926a 100644 --- a/examples/test_iot_led_driver.py +++ b/examples/test_iot_led_driver.py @@ -12,7 +12,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground()) self.pwr = self.Port( VoltageSource( - voltage_out=(10, 16) * Volt, + voltage=(10, 16) * Volt, current_limits=(0, 3) * Amp, ) ) diff --git a/examples/test_iot_thermal_camera.py b/examples/test_iot_thermal_camera.py index 63b5161c7..fd47f25e4 100644 --- a/examples/test_iot_thermal_camera.py +++ b/examples/test_iot_thermal_camera.py @@ -283,8 +283,8 @@ def __init__(self) -> None: ) self.vdd = self.Port(VoltageSink(voltage_limits=(2.97, 3.63) * Volt)) - self.v1v20 = self.Port(VoltageSource(voltage_out=1.2 * Volt(tol=0), current_limits=0 * Amp(tol=0))) - self.tocap = self.Port(VoltageSource(voltage_out=self.avdd.link().voltage)) # assumed, not documented + self.v1v20 = self.Port(VoltageSource(voltage=1.2 * Volt(tol=0), current_limits=0 * Amp(tol=0))) + self.tocap = self.Port(VoltageSource(voltage=self.avdd.link().voltage)) # assumed, not documented self.exres1 = self.Port(AnalogSource.from_supply(self.gnd, self.avdd)) # assumed, not documented self.crystal = self.Port(CrystalDriver(frequency_limits=25 * MHertz(tol=30e-6))) # TODO also support CLKIN @@ -558,7 +558,7 @@ def generate(self) -> None: self.connect( self.poe.pos.adapt_to( VoltageSource( - voltage_out=(POE_VOUT_MIN, POE_VOUT_MAX) * Volt, current_limits=(0, output_power_max / POE_VOUT_MAX) + voltage=(POE_VOUT_MIN, POE_VOUT_MAX) * Volt, current_limits=(0, output_power_max / POE_VOUT_MAX) ) ), self.ic.vdd, diff --git a/examples/test_multimeter.py b/examples/test_multimeter.py index 0a44e31c4..201cad1ab 100644 --- a/examples/test_multimeter.py +++ b/examples/test_multimeter.py @@ -87,7 +87,7 @@ def contents(self) -> None: conversions={ "input_positive": AnalogSink(), "output": AnalogSource( # assumed clamped by the switch in the resistor mux - voltage_out=output_voltage, + voltage=output_voltage, signal=output_voltage, current_limits=(-10, 10) * mAmp, impedance=1 * mOhm(tol=0), @@ -166,7 +166,7 @@ def contents(self) -> None: ) # approx lowest resistance - TODO properly model the resistor mux ), "range.sw": AnalogSource( - voltage_out=(0, max_in_voltage), + voltage=(0, max_in_voltage), signal=(0, max_in_voltage), impedance=(1, 1000) * kOhm, # TODO properly model resistor mux ), @@ -311,7 +311,7 @@ def contents(self) -> None: self.inp = self.Block(BananaSafetyJack()) inp_port = self.inp.port.adapt_to( AnalogSource( - voltage_out=VOLTAGE_RATING, + voltage=VOLTAGE_RATING, signal=VOLTAGE_RATING, current_limits=(0, 10) * mAmp, impedance=(0, 100) * Ohm, diff --git a/examples/test_robotcrawler.py b/examples/test_robotcrawler.py index f17927f56..8f2b3110f 100644 --- a/examples/test_robotcrawler.py +++ b/examples/test_robotcrawler.py @@ -20,7 +20,7 @@ def __init__(self) -> None: self.pwm = self.Port(DigitalSink(), [Input]) # no specs given self.fb = self.Port( AnalogSource( # no specs given - voltage_out=(0.9, 2.1) + voltage=(0.9, 2.1) * Volt, # from https://www.pololu.com/blog/814/new-products-special-servos-with-position-feedback signal=(0.9, 2.1) * Volt, ) diff --git a/examples/test_tofarray.py b/examples/test_tofarray.py index eddde7853..8dca22d0a 100644 --- a/examples/test_tofarray.py +++ b/examples/test_tofarray.py @@ -12,7 +12,7 @@ def __init__(self) -> None: self.pwr = self.Port( VoltageSource( - voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick? + voltage=(7, 14) * Volt, # TODO get limits from CAN power brick? current_limits=(0, 0.15) * Amp, # TODO get actual limits from ??? ), optional=True, diff --git a/examples/test_usb_source_measure.py b/examples/test_usb_source_measure.py index 5a3c92540..45c82a8c4 100644 --- a/examples/test_usb_source_measure.py +++ b/examples/test_usb_source_measure.py @@ -222,7 +222,7 @@ def contents(self) -> None: ), ), "out": VoltageSource( - voltage_out=self.pwr.link().voltage, + voltage=self.pwr.link().voltage, current_limits=self.high_fet.actual_drain_current_rating.intersect( self.low_fet.actual_drain_current_rating ), @@ -331,7 +331,7 @@ def generate(self) -> None: if dir: self.diode = self.Block( Diode( # TODO should be encoded as a voltage difference? - reverse_voltage=self.amp.out.voltage_out, + reverse_voltage=self.amp.out.voltage, current=RangeExpr.ZERO, # an approximation, current rating not significant here voltage_drop=(0, 0.8) * Volt, # arbitrary low threshold ) @@ -369,7 +369,7 @@ def generate(self) -> None: ), "actual": AnalogSink(impedance=self.rtop.actual_resistance + self.rbot.actual_resistance), "rtop.2": AnalogSource( - voltage_out=self.target.link().voltage.hull(self.actual.link().voltage), + voltage=self.target.link().voltage.hull(self.actual.link().voltage), signal=self.target.link().voltage.hull(self.actual.link().voltage), impedance=1 / (1 / self.rtop.actual_resistance + 1 / self.rbot.actual_resistance), ), @@ -428,7 +428,7 @@ def contents(self) -> None: current_draw=self.output.link().current_draw, impedance=self.output.link().sink_impedance ), "output": AnalogSource( - voltage_out=self.input.link().voltage.intersect(self.model_voltage_clamp), + voltage=self.input.link().voltage.intersect(self.model_voltage_clamp), signal=self.input.link().signal.intersect(self.model_signal_clamp), impedance=self.input.link().source_impedance, ), @@ -524,7 +524,7 @@ def contents(self) -> None: # USB PD port that supplies power to the load # USB PD can't actually do 8 A, but this suppresses the error and we can software-limit current draw - self.usb = self.Block(UsbCReceptacle(voltage_out=(5, 20) * Volt, current_limits=(0, 8) * Amp)) + self.usb = self.Block(UsbCReceptacle(voltage=(5, 20) * Volt, current_limits=(0, 8) * Amp)) self.gnd = self.connect(self.usb.gnd) self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd) From 42402f913603aa14f587a440605888e1762c0cea Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Thu, 25 Jun 2026 00:07:09 -0700 Subject: [PATCH 20/23] Update __init__.py --- edg/util/__init__.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/edg/util/__init__.py b/edg/util/__init__.py index 0ea9d05eb..85ae5096e 100644 --- a/edg/util/__init__.py +++ b/edg/util/__init__.py @@ -1,21 +1,20 @@ import warnings from functools import wraps -from typing import Tuple, Callable, ParamSpec, TypeVar, Any +from typing import Tuple, Callable, TypeVar, Any -P = ParamSpec("P") -R = TypeVar("R") +CallableType = TypeVar("CallableType", bound=Callable[..., Any]) -def deprecated_param_remap(*params: Tuple[str, str]) -> Callable[[Callable[P, R]], Callable[P, R]]: +def deprecated_param_remap(*params: Tuple[str, str]) -> Callable[[CallableType], CallableType]: """Decorator to remap deprecated parameter names to new names. Args: *params: A list of tuples where each tuple contains the old parameter name and the new parameter name. """ - def decorator(func: Callable[P, R]) -> Callable[P, R]: + def decorator(func: CallableType) -> CallableType: @wraps(func) - def wrapper(self: Any, *args: Any, **kwargs: Any) -> R: + def wrapper(self: Any, *args: Any, **kwargs: Any) -> Any: for old_param, new_param in params: if old_param in kwargs: warnings.warn( From 5df649cef0b0fca3c8fb749f3e0bca6ae29bee9c Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Thu, 25 Jun 2026 00:07:53 -0700 Subject: [PATCH 21/23] cleanup type errors --- edg/electronics_interfaces/AnalogPort.py | 2 +- edg/electronics_interfaces/DigitalPorts.py | 8 ++++---- edg/electronics_interfaces/VoltagePorts.py | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/edg/electronics_interfaces/AnalogPort.py b/edg/electronics_interfaces/AnalogPort.py index 835049a9b..182ebc26d 100644 --- a/edg/electronics_interfaces/AnalogPort.py +++ b/edg/electronics_interfaces/AnalogPort.py @@ -252,7 +252,7 @@ def from_supply( else: # generic default signal = supply_range - return AnalogSource(voltage=supply_range, signal=signal, current_limits=current_limits, impedance=impedance) + return AnalogSource(voltage=supply_range, signal=signal, current_limits=current_limits, impedance=impedance) # type: ignore @deprecated_param_remap(("voltage_out", "voltage"), ("signal_out", "signal")) def __init__( diff --git a/edg/electronics_interfaces/DigitalPorts.py b/edg/electronics_interfaces/DigitalPorts.py index 8a6d6bf01..a7605f1c9 100644 --- a/edg/electronics_interfaces/DigitalPorts.py +++ b/edg/electronics_interfaces/DigitalPorts.py @@ -357,13 +357,13 @@ def from_supply( else: output_threshold = (GroundLink._voltage_range(neg).upper(), VoltageLink._voltage_range(pos).lower()) - return DigitalSource(voltage=supply_range, current_limits=current_limits, output_thresholds=output_threshold) + return DigitalSource(voltage=supply_range, current_limits=current_limits, output_thresholds=output_threshold) # type: ignore @staticmethod def from_bidir(model: DigitalBidir) -> DigitalSource: model_is_empty = not model._get_initializers([]) if not model_is_empty: # DigitalSource has additional high_driver and low_driver fields - return DigitalSource( + return DigitalSource( # type: ignore model.voltage, model.current_limits, output_thresholds=model.output_thresholds, @@ -371,7 +371,7 @@ def from_bidir(model: DigitalBidir) -> DigitalSource: pulldown_capable=model.pulldown_capable, ) else: - return DigitalSource.empty() + return DigitalSource.empty() # type: ignore @deprecated_param_remap(("voltage_out", "voltage")) def __init__( @@ -579,7 +579,7 @@ def from_supply( else: # assumed ideal output_threshold = (neg_base, VoltageLink._voltage_range(pos).lower()) - return DigitalBidir( # TODO get rid of to_expr_type w/ dedicated Range conversion + return DigitalBidir( # type: ignore voltage_limits=voltage_limit, current_draw=current_draw, voltage=supply_range, diff --git a/edg/electronics_interfaces/VoltagePorts.py b/edg/electronics_interfaces/VoltagePorts.py index 4131db299..329ebca0d 100644 --- a/edg/electronics_interfaces/VoltagePorts.py +++ b/edg/electronics_interfaces/VoltagePorts.py @@ -19,7 +19,7 @@ class VoltageLink(Link): def _voltage_range(cls, port: Port[VoltageLink]) -> RangeExpr: """Returns the voltage for a Voltage port, either sink or source""" if isinstance(port, VoltageSource): - return port.voltage + return port.voltage # type: ignore elif isinstance(port, VoltageSink): return port.link().voltage else: From 71624fd8e280ca9b05a60de226b9836df575bc4e Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Thu, 25 Jun 2026 00:14:43 -0700 Subject: [PATCH 22/23] blacken --- edg/abstract_parts/IoControllerInterfaceMixins.py | 4 +--- edg/circuits/ResistiveSensor.py | 4 +--- edg/circuits/SwitchMatrix.py | 3 +-- edg/parts/microcontroller/Rp2040.py | 4 +--- edg/parts/power/converter/TexasInstruments_Boost.py | 4 +--- edg/parts/sensor/Mag_A1304.py | 4 +--- examples/test_high_switch.py | 4 +--- 7 files changed, 7 insertions(+), 20 deletions(-) diff --git a/edg/abstract_parts/IoControllerInterfaceMixins.py b/edg/abstract_parts/IoControllerInterfaceMixins.py index f9c1be16f..0269da830 100644 --- a/edg/abstract_parts/IoControllerInterfaceMixins.py +++ b/edg/abstract_parts/IoControllerInterfaceMixins.py @@ -147,9 +147,7 @@ def _generate_gnd_node(self) -> Ground: return self.gnd_model.io @deprecated_param_remap(("voltage_out", "voltage")) - def _generate_pwr_node( - self, voltage: RangeLike, current_limits: RangeLike - ) -> Union[VoltageSink, VoltageSource]: + def _generate_pwr_node(self, voltage: RangeLike, current_limits: RangeLike) -> Union[VoltageSink, VoltageSource]: """Helper function that returns a power node, either directly taking the pwr port if available, or generating an internal voltage node and optionally connecting it to pwr_out (if used). diff --git a/edg/circuits/ResistiveSensor.py b/edg/circuits/ResistiveSensor.py index e30438a6f..2f6ddf999 100644 --- a/edg/circuits/ResistiveSensor.py +++ b/edg/circuits/ResistiveSensor.py @@ -16,9 +16,7 @@ def __init__(self, resistance_range: RangeLike, fixed_resistance: RangeLike) -> self.fixed_resistance = self.ArgParameter(fixed_resistance) self.input = self.Port(VoltageSink(current_draw=RangeExpr()), [Power]) - self.output = self.Port( - AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr()), [Output] - ) + self.output = self.Port(AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=RangeExpr()), [Output]) self.gnd = self.Port(Ground(), [Common]) # TODO deduplicate with ResistiveDivider class diff --git a/edg/circuits/SwitchMatrix.py b/edg/circuits/SwitchMatrix.py index b22fa421c..21af7a03e 100644 --- a/edg/circuits/SwitchMatrix.py +++ b/edg/circuits/SwitchMatrix.py @@ -27,8 +27,7 @@ def contents(self) -> None: self.col.init_from( DigitalSource( # diode anode, externally pulled, driven to col by switch closure - voltage=self.row.link().voltage.lower() - + self.voltage_drop, # use spec to avoid circular dependency + voltage=self.row.link().voltage.lower() + self.voltage_drop, # use spec to avoid circular dependency output_thresholds=(self.row.link().voltage + self.voltage_drop).hull(float("inf")), low_driver=True, high_driver=False, diff --git a/edg/parts/microcontroller/Rp2040.py b/edg/parts/microcontroller/Rp2040.py index 599425734..77cf1fe72 100644 --- a/edg/parts/microcontroller/Rp2040.py +++ b/edg/parts/microcontroller/Rp2040.py @@ -119,9 +119,7 @@ def __init__(self, **kwargs: Any) -> None: self.qspi_sd3 = self.Port(self._dio_std_model, optional=self._model) self.xosc = self.Port( - CrystalDriver( - frequency_limits=(1, 15) * MHertz, voltage=self.iovdd.link().voltage # datasheet 2.15.2.2 - ), + CrystalDriver(frequency_limits=(1, 15) * MHertz, voltage=self.iovdd.link().voltage), # datasheet 2.15.2.2 optional=True, ) diff --git a/edg/parts/power/converter/TexasInstruments_Boost.py b/edg/parts/power/converter/TexasInstruments_Boost.py index 6392b3dfb..679fe5e14 100644 --- a/edg/parts/power/converter/TexasInstruments_Boost.py +++ b/edg/parts/power/converter/TexasInstruments_Boost.py @@ -286,6 +286,4 @@ def contents(self) -> None: ), ) - self.require( - self.pwr_out.voltage.upper() + self.rect.actual_voltage_drop.upper() <= 40, "max SW voltage" - ) + self.require(self.pwr_out.voltage.upper() + self.rect.actual_voltage_drop.upper() <= 40, "max SW voltage") diff --git a/edg/parts/sensor/Mag_A1304.py b/edg/parts/sensor/Mag_A1304.py index 366bd1ffc..505615db6 100644 --- a/edg/parts/sensor/Mag_A1304.py +++ b/edg/parts/sensor/Mag_A1304.py @@ -16,9 +16,7 @@ def __init__(self) -> None: ) ) self.vout = self.Port( - AnalogSource.from_supply( - self.gnd, self.vcc, signal_abs=(0.38, 2.87) # output saturation limits @ Vcc=3.3v - ) + AnalogSource.from_supply(self.gnd, self.vcc, signal_abs=(0.38, 2.87)) # output saturation limits @ Vcc=3.3v ) @override diff --git a/examples/test_high_switch.py b/examples/test_high_switch.py index ba2eb9dd1..c8f66c90c 100644 --- a/examples/test_high_switch.py +++ b/examples/test_high_switch.py @@ -83,9 +83,7 @@ def __init__(self) -> None: super().__init__() self.pwr = self.Port( - VoltageSource( - voltage=12 * Volt(tol=0.1), current_limits=(0, 3) * Amp # TODO get actual limits from LVPDB? - ) + VoltageSource(voltage=12 * Volt(tol=0.1), current_limits=(0, 3) * Amp) # TODO get actual limits from LVPDB? ) self.gnd = self.Port(Ground()) From 12a8d6ff45ed8e4c1b5394112a41e57d8e290974 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Thu, 25 Jun 2026 00:24:20 -0700 Subject: [PATCH 23/23] cleaning --- edg/parts/connector/Connectors.py | 4 ++-- edg/util/__init__.py | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/edg/parts/connector/Connectors.py b/edg/parts/connector/Connectors.py index 875b377d5..555e61e6a 100644 --- a/edg/parts/connector/Connectors.py +++ b/edg/parts/connector/Connectors.py @@ -27,7 +27,7 @@ class Pj_102ah(PowerBarrelJack, FootprintBlock): def contents(self) -> None: super().contents() self.require(self.pwr.voltage.within((0, 24) * Volt)) # datasheet ratings for connector - self.require(self.pwr.current_limits.within((0, 2.5) * Volt)) + self.require(self.pwr.current_limits.within((0, 2.5) * Amp)) self.footprint( "J", "Connector_BarrelJack:BarrelJack_CUI_PJ-102AH_Horizontal", @@ -49,7 +49,7 @@ class Pj_036ah(PowerBarrelJack, FootprintBlock): def contents(self) -> None: super().contents() self.require(self.pwr.voltage.within((0, 24) * Volt)) # datasheet ratings for connector - self.require(self.pwr.current_limits.within((0, 5) * Volt)) + self.require(self.pwr.current_limits.within((0, 5) * Amp)) self.footprint( "J", diff --git a/edg/util/__init__.py b/edg/util/__init__.py index 85ae5096e..f2753b1c4 100644 --- a/edg/util/__init__.py +++ b/edg/util/__init__.py @@ -14,7 +14,7 @@ def deprecated_param_remap(*params: Tuple[str, str]) -> Callable[[CallableType], def decorator(func: CallableType) -> CallableType: @wraps(func) - def wrapper(self: Any, *args: Any, **kwargs: Any) -> Any: + def wrapper(*args: Any, **kwargs: Any) -> Any: for old_param, new_param in params: if old_param in kwargs: warnings.warn( @@ -22,9 +22,10 @@ def wrapper(self: Any, *args: Any, **kwargs: Any) -> Any: DeprecationWarning, stacklevel=2, ) - assert new_param not in kwargs, f"both old {old_param} and new {new_param} parameters specified" + if new_param in kwargs: + raise ValueError(f"both old {old_param} and new {new_param} parameters specified") kwargs[new_param] = kwargs.pop(old_param) - return func(self, *args, **kwargs) + return func(*args, **kwargs) return wrapper # type: ignore