From 060cf930a44a90fa4626da254f4e492776be374b Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com> Date: Sun, 4 Oct 2026 20:30:43 +0300 Subject: [PATCH 1/3] hisi: give gk7205v500/v510/v530 their own pad table The V500-family chips were handed EV200regs. They share ev200's iocfg addresses but not its selectors, so ipctool reginfo named the wrong functions on them, and a consumer asking for a PWM pad (majestic's PWM backlight) found none past PWM3: the IR lamps of a GK7205V510 PTZ camera sit on PWM8 and PWM9, which the ev200 table calls LCD_DATA4 and "reserved". V500regs is generated from XMedia's PIN_OUT_V510.xlsx: sheet 1 gives each pin's function numbers, which are the selector values, and sheet 3 the register addresses. PIN_OUT_V530.xlsx agrees on all 93 rows but one, where it adds FMC_STARTUP_DISABLE as selector 2 of UART0_TXD, and that is merged in. The QFN V330/V230 pin-outs are strict subsets. iocfg_reg0-5 are the power-sequencing pins and have no selector. reginfo_test checks PWM8/PWM9/PWM11 resolve to the right pads and selectors, that pad 56 no longer offers LCD_DATA4, and V510 joins the table-integrity sweep. --- src/padmux_names.c | 27 ++++-- src/padmux_names.h | 54 ++++++++--- src/reginfo.c | 225 ++++++++++++++++++++++++++++++++++++++++++++- src/reginfo_test.c | 39 ++++++++ 4 files changed, 326 insertions(+), 19 deletions(-) diff --git a/src/padmux_names.c b/src/padmux_names.c index d5bb5017..6fcba314 100644 --- a/src/padmux_names.c +++ b/src/padmux_names.c @@ -364,6 +364,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .FLASH_TRIG = "FLASH_TRIG", #endif +#if defined(IPCHW_PADMUX_V4) + .FMC_STARTUP_DISABLE = "FMC_STARTUP_DISABLE", +#endif #if defined(IPCHW_PADMUX_SSTAR) .FUART_2W_MODE_1 = "FUART_2W_MODE_1", #endif @@ -796,7 +799,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .GPIO9_1 = "GPIO9_1", #endif -#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .GPIO9_2 = "GPIO9_2", #endif #if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) @@ -1129,7 +1132,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) .I2S_WS_TX = "I2S_WS_TX", #endif -#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) +#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .IR_IN = "IR_IN", #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3670,6 +3673,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .PWM1 = "PWM1", #endif +#if defined(IPCHW_PADMUX_V4) + .PWM10 = "PWM10", +#endif #if defined(IPCHW_PADMUX_SSTAR) .PWM10_MODE_1 = "PWM10_MODE_1", #endif @@ -3682,6 +3688,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_SSTAR) .PWM10_MODE_4 = "PWM10_MODE_4", #endif +#if defined(IPCHW_PADMUX_V4) + .PWM11 = "PWM11", +#endif #if defined(IPCHW_PADMUX_SSTAR) .PWM1_MODE_1 = "PWM1_MODE_1", #endif @@ -3775,7 +3784,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .PWM3_PC = "PWM3_PC", #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) .PWM4 = "PWM4", #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3799,7 +3808,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .PWM4_PC = "PWM4_PC", #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) .PWM5 = "PWM5", #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3823,7 +3832,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .PWM5_PC = "PWM5_PC", #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) .PWM6 = "PWM6", #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3847,7 +3856,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .PWM6_PD = "PWM6_PD", #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) .PWM7 = "PWM7", #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3871,6 +3880,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .PWM7_PD = "PWM7_PD", #endif +#if defined(IPCHW_PADMUX_V4) + .PWM8 = "PWM8", +#endif #if defined(IPCHW_PADMUX_SSTAR) .PWM8_MODE_1 = "PWM8_MODE_1", #endif @@ -3895,6 +3907,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_SSTAR) .PWM8_MODE_8 = "PWM8_MODE_8", #endif +#if defined(IPCHW_PADMUX_V4) + .PWM9 = "PWM9", +#endif #if defined(IPCHW_PADMUX_SSTAR) .PWM9_MODE_1 = "PWM9_MODE_1", #endif diff --git a/src/padmux_names.h b/src/padmux_names.h index 905a879c..d955dc72 100644 --- a/src/padmux_names.h +++ b/src/padmux_names.h @@ -370,6 +370,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char FLASH_TRIG[sizeof "FLASH_TRIG"]; #endif +#if defined(IPCHW_PADMUX_V4) + char FMC_STARTUP_DISABLE[sizeof "FMC_STARTUP_DISABLE"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char FUART_2W_MODE_1[sizeof "FUART_2W_MODE_1"]; #endif @@ -802,7 +805,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char GPIO9_1[sizeof "GPIO9_1"]; #endif -#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char GPIO9_2[sizeof "GPIO9_2"]; #endif #if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) @@ -1135,7 +1138,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) char I2S_WS_TX[sizeof "I2S_WS_TX"]; #endif -#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) +#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char IR_IN[sizeof "IR_IN"]; #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3676,6 +3679,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char PWM1[sizeof "PWM1"]; #endif +#if defined(IPCHW_PADMUX_V4) + char PWM10[sizeof "PWM10"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char PWM10_MODE_1[sizeof "PWM10_MODE_1"]; #endif @@ -3688,6 +3694,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_SSTAR) char PWM10_MODE_4[sizeof "PWM10_MODE_4"]; #endif +#if defined(IPCHW_PADMUX_V4) + char PWM11[sizeof "PWM11"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char PWM1_MODE_1[sizeof "PWM1_MODE_1"]; #endif @@ -3781,7 +3790,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char PWM3_PC[sizeof "PWM3_PC"]; #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) char PWM4[sizeof "PWM4"]; #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3805,7 +3814,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char PWM4_PC[sizeof "PWM4_PC"]; #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) char PWM5[sizeof "PWM5"]; #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3829,7 +3838,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char PWM5_PC[sizeof "PWM5_PC"]; #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) char PWM6[sizeof "PWM6"]; #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3853,7 +3862,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char PWM6_PD[sizeof "PWM6_PD"]; #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) char PWM7[sizeof "PWM7"]; #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -3877,6 +3886,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char PWM7_PD[sizeof "PWM7_PD"]; #endif +#if defined(IPCHW_PADMUX_V4) + char PWM8[sizeof "PWM8"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char PWM8_MODE_1[sizeof "PWM8_MODE_1"]; #endif @@ -3901,6 +3913,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_SSTAR) char PWM8_MODE_8[sizeof "PWM8_MODE_8"]; #endif +#if defined(IPCHW_PADMUX_V4) + char PWM9[sizeof "PWM9"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char PWM9_MODE_1[sizeof "PWM9_MODE_1"]; #endif @@ -6433,6 +6448,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_FLASH_TRIG ((uint16_t)offsetof(struct padmux_names, FLASH_TRIG)) #endif +#if defined(IPCHW_PADMUX_V4) +#define PMX_FMC_STARTUP_DISABLE ((uint16_t)offsetof(struct padmux_names, FMC_STARTUP_DISABLE)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_FUART_2W_MODE_1 ((uint16_t)offsetof(struct padmux_names, FUART_2W_MODE_1)) #endif @@ -6865,7 +6883,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_GPIO9_1 ((uint16_t)offsetof(struct padmux_names, GPIO9_1)) #endif -#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_GPIO9_2 ((uint16_t)offsetof(struct padmux_names, GPIO9_2)) #endif #if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) @@ -7198,7 +7216,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) #define PMX_I2S_WS_TX ((uint16_t)offsetof(struct padmux_names, I2S_WS_TX)) #endif -#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) +#if defined(IPCHW_PADMUX_3536C) || defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_IR_IN ((uint16_t)offsetof(struct padmux_names, IR_IN)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -9739,6 +9757,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_PWM1 ((uint16_t)offsetof(struct padmux_names, PWM1)) #endif +#if defined(IPCHW_PADMUX_V4) +#define PMX_PWM10 ((uint16_t)offsetof(struct padmux_names, PWM10)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM10_MODE_1 ((uint16_t)offsetof(struct padmux_names, PWM10_MODE_1)) #endif @@ -9751,6 +9772,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM10_MODE_4 ((uint16_t)offsetof(struct padmux_names, PWM10_MODE_4)) #endif +#if defined(IPCHW_PADMUX_V4) +#define PMX_PWM11 ((uint16_t)offsetof(struct padmux_names, PWM11)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM1_MODE_1 ((uint16_t)offsetof(struct padmux_names, PWM1_MODE_1)) #endif @@ -9844,7 +9868,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_PWM3_PC ((uint16_t)offsetof(struct padmux_names, PWM3_PC)) #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) #define PMX_PWM4 ((uint16_t)offsetof(struct padmux_names, PWM4)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -9868,7 +9892,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_PWM4_PC ((uint16_t)offsetof(struct padmux_names, PWM4_PC)) #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) #define PMX_PWM5 ((uint16_t)offsetof(struct padmux_names, PWM5)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -9892,7 +9916,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_PWM5_PC ((uint16_t)offsetof(struct padmux_names, PWM5_PC)) #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) #define PMX_PWM6 ((uint16_t)offsetof(struct padmux_names, PWM6)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -9916,7 +9940,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_PWM6_PD ((uint16_t)offsetof(struct padmux_names, PWM6_PD)) #endif -#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) +#if defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) #define PMX_PWM7 ((uint16_t)offsetof(struct padmux_names, PWM7)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -9940,6 +9964,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_PWM7_PD ((uint16_t)offsetof(struct padmux_names, PWM7_PD)) #endif +#if defined(IPCHW_PADMUX_V4) +#define PMX_PWM8 ((uint16_t)offsetof(struct padmux_names, PWM8)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM8_MODE_1 ((uint16_t)offsetof(struct padmux_names, PWM8_MODE_1)) #endif @@ -9964,6 +9991,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM8_MODE_8 ((uint16_t)offsetof(struct padmux_names, PWM8_MODE_8)) #endif +#if defined(IPCHW_PADMUX_V4) +#define PMX_PWM9 ((uint16_t)offsetof(struct padmux_names, PWM9)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_PWM9_MODE_1 ((uint16_t)offsetof(struct padmux_names, PWM9_MODE_1)) #endif diff --git a/src/reginfo.c b/src/reginfo.c index a76ce958..49812143 100644 --- a/src/reginfo.c +++ b/src/reginfo.c @@ -2111,6 +2111,229 @@ static const muxctrl_reg_t *DV200regs[] = { &DV200_iocfg_reg96, &DV200_iocfg_reg97, &DV200_iocfg_reg98, 0, }; + +/* GK7205V500 / V510 / V530 (XMedia XM720xxx). Not an ev200: the pads sit at + * the same iocfg addresses but behind different selectors, and the block has + * twelve PWM channels, not four. Generated from XMedia's PIN_OUT_V510.xlsx + * (sheet 1, "Function Number" per pin; addresses from sheet 3), plus the one + * selector PIN_OUT_V530.xlsx adds (FMC_STARTUP_DISABLE on UART0_TXD). The two + * workbooks agree on every other row; the QFN V330/V230 pin-outs are strict + * subsets of it. iocfg_reg0-5 are the power-sequencing pins, which have no + * selector. */ +MUXCTRL(V500_iocfg_reg6, 0x112C0074, PMX_GPIO6_4, PMX_reserved, PMX_UART1_TXD, + PMX_I2C1_SCL, PMX_reserved, PMX_PWM11, PMX_reserved, PMX_SPI0_SCLK) +MUXCTRL(V500_iocfg_reg7, 0x112C0070, PMX_GPIO6_5, PMX_VI_BT1120_DATA2, + PMX_UART1_RXD, PMX_I2C1_SDA, PMX_reserved, PMX_PWM10, PMX_reserved, + PMX_SPI0_SDI) +MUXCTRL(V500_iocfg_reg8, 0x112C006C, PMX_GPIO6_6, PMX_SFC_BOOT_MODE, PMX_PWM3, + PMX_reserved, PMX_reserved, PMX_UART2_TXD, PMX_reserved, PMX_SPI0_SDO) +MUXCTRL(V500_iocfg_reg9, 0x112C0068, PMX_GPIO6_7, PMX_VI_BT1120_DATA3, PMX_PWM9, + PMX_reserved, PMX_reserved, PMX_UART2_RXD, PMX_reserved, PMX_SPI0_CSN) +MUXCTRL(V500_iocfg_reg10, 0x112C0058, PMX_GPIO7_0, PMX_VI_BT1120_DATA4, + PMX_I2C2_SCL, PMX_reserved, PMX_SDIO1_CDATA3, PMX_PWM8, PMX_reserved, + PMX_SPI1_CSN1) +MUXCTRL(V500_iocfg_reg11, 0x112C005C, PMX_GPIO7_1, PMX_VI_BT1120_DATA5, + PMX_I2C2_SDA, PMX_reserved, PMX_SDIO1_CDATA2, PMX_PWM7, PMX_reserved, + PMX_VI_DATA0) +MUXCTRL(V500_iocfg_reg12, 0x112C0060, PMX_GPIO7_2, PMX_VI_BT1120_CLK, + PMX_I2C0_SDA, PMX_reserved, PMX_SDIO1_CDATA1, PMX_PWM6, PMX_reserved, + PMX_VI_DATA1) +MUXCTRL(V500_iocfg_reg13, 0x112C0064, PMX_GPIO7_3, PMX_reserved, PMX_I2C0_SCL, + PMX_reserved, PMX_SDIO1_CDATA0, PMX_PWM5, PMX_reserved, PMX_VI_DATA2) +MUXCTRL(V500_iocfg_reg14, 0x112C0078, PMX_GPIO7_4, PMX_UART1_TXD) +MUXCTRL(V500_iocfg_reg15, 0x112C007C, PMX_GPIO7_5, PMX_UART1_RXD) +MUXCTRL(V500_iocfg_reg16, 0x112C0080, PMX_GPIO7_6, PMX_UART1_CTSN) +MUXCTRL(V500_iocfg_reg17, 0x112C0084, PMX_GPIO7_7, PMX_UART1_RTSN) +MUXCTRL(V500_iocfg_reg18, 0x112C0088, PMX_GPIO8_0) +MUXCTRL(V500_iocfg_reg19, 0x112C008C, PMX_GPIO8_1) +MUXCTRL(V500_iocfg_reg20, 0x112C0090, PMX_GPIO8_2) +MUXCTRL(V500_iocfg_reg21, 0x112C0094, PMX_GPIO8_3) +MUXCTRL(V500_iocfg_reg22, 0x112C0054, PMX_GPIO8_4, PMX_BOOT_SEL0, + PMX_SENSOR_CLK, PMX_PWM2, PMX_reserved, PMX_reserved, PMX_reserved, + PMX_SPI1_CSN0) +MUXCTRL(V500_iocfg_reg23, 0x112C004C, PMX_GPIO8_5, PMX_VI_BT1120_DATA0, + PMX_VI_HS, PMX_reserved, PMX_SDIO1_CCMD, PMX_PWM4, PMX_reserved, + PMX_SPI1_SDI) +MUXCTRL(V500_iocfg_reg24, 0x112C0050, PMX_GPIO8_6, PMX_VI_BT1120_DATA1, + PMX_VI_VS, PMX_reserved, PMX_reserved, PMX_reserved, PMX_reserved, + PMX_SPI1_SDO) +MUXCTRL(V500_iocfg_reg25, 0x112C0048, PMX_GPIO8_7, PMX_BOOT_SEL1, + PMX_SENSOR_RSTN, PMX_reserved, PMX_SDIO1_CCLK_OUT, PMX_reserved, + PMX_reserved, PMX_SPI1_SCLK) +MUXCTRL(V500_iocfg_reg26, 0x112C0098, PMX_GPIO5_2, PMX_FLASH_TRIG, + PMX_SENSOR_HS) +MUXCTRL(V500_iocfg_reg27, 0x112C009C, PMX_GPIO5_3, PMX_SHUTTER_TRIG, + PMX_SENSOR_VS, PMX_reserved, PMX_SPI0_CSN) +MUXCTRL(V500_iocfg_reg28, 0x112C00A0, PMX_GPIO6_0, PMX_I2C1_SDA, PMX_reserved, + PMX_reserved, PMX_SPI0_SDO) +MUXCTRL(V500_iocfg_reg29, 0x112C00A4, PMX_GPIO6_1, PMX_I2C1_SCL, PMX_reserved, + PMX_reserved, PMX_SPI0_SCLK) +MUXCTRL(V500_iocfg_reg30, 0x112C0040, PMX_GPIO5_0, PMX_ETH_LINK_STA_LED, + PMX_VI_DATA0, PMX_VI_DATA2, PMX_reserved, PMX_reserved, PMX_reserved, + PMX_SPI0_CSN) +MUXCTRL(V500_iocfg_reg31, 0x112C0044, PMX_GPIO5_1, PMX_ETH_LINK_ACT_LED, + PMX_TEST_MODE) +MUXCTRL(V500_iocfg_reg32, 0x112C0028, PMX_TEST_CLK, PMX_SENSOR_CLK, + PMX_VI_DATA6, PMX_reserved, PMX_GPIO5_4) +MUXCTRL(V500_iocfg_reg33, 0x112C002C, PMX_GPIO5_5, PMX_SENSOR_RSTN, + PMX_VI_DATA4) +MUXCTRL(V500_iocfg_reg34, 0x112C0030, PMX_GPIO5_6, PMX_I2C0_SDA, PMX_VI_DATA3) +MUXCTRL(V500_iocfg_reg35, 0x112C0034, PMX_GPIO5_7, PMX_I2C0_SCL, PMX_VI_DATA5) +MUXCTRL(V500_iocfg_reg36, 0x112C0038, PMX_GPIO6_2, PMX_I2C2_SDA, PMX_VI_DATA2, + PMX_VI_HS, PMX_reserved, PMX_reserved, PMX_reserved, PMX_SPI0_SDO) +MUXCTRL(V500_iocfg_reg37, 0x112C003C, PMX_GPIO6_3, PMX_I2C2_SCL, PMX_VI_DATA1, + PMX_VI_VS, PMX_reserved, PMX_reserved, PMX_reserved, PMX_SPI0_SCLK) +MUXCTRL(V500_iocfg_reg38, 0x112C0014, PMX_MIPI_RX_D2P, PMX_VI_BT1120_DATA15, + PMX_VI_DATA10, PMX_VI_DATA11) +MUXCTRL(V500_iocfg_reg39, 0x112C0010, PMX_MIPI_RX_D2N, PMX_VI_BT1120_DATA14, + PMX_VI_DATA11, PMX_VI_DATA10) +MUXCTRL(V500_iocfg_reg40, 0x112C000C, PMX_MIPI_RX_D0P, PMX_VI_BT1120_DATA13, + PMX_VI_DATA9, PMX_VI_DATA8) +MUXCTRL(V500_iocfg_reg41, 0x112C0008, PMX_MIPI_RX_D0N, PMX_VI_BT1120_DATA12, + PMX_VI_DATA8, PMX_VI_DATA9) +MUXCTRL(V500_iocfg_reg42, 0x112C0004, PMX_MIPI_RX_CK0P, PMX_VI_BT1120_DATA11, + PMX_VI_DATA7) +MUXCTRL(V500_iocfg_reg43, 0x112C0000, PMX_MIPI_RX_CK0N, PMX_VI_BT1120_DATA10, + PMX_VI_CLK) +MUXCTRL(V500_iocfg_reg44, 0x112C0024, PMX_MIPI_RX_D3P, PMX_VI_BT1120_DATA9, + PMX_reserved, PMX_VI_DATA5) +MUXCTRL(V500_iocfg_reg45, 0x112C0020, PMX_MIPI_RX_D3N, PMX_VI_BT1120_DATA8, + PMX_reserved, PMX_VI_DATA3) +MUXCTRL(V500_iocfg_reg46, 0x112C001C, PMX_MIPI_RX_D1P, PMX_VI_BT1120_DATA7, + PMX_reserved, PMX_VI_DATA4) +MUXCTRL(V500_iocfg_reg47, 0x112C0018, PMX_MIPI_RX_D1N, PMX_VI_BT1120_DATA6, + PMX_reserved, PMX_VI_DATA6) +MUXCTRL(V500_iocfg_reg48, 0x100C0084, PMX_GPIO2_4, PMX_SPI1_SCLK) +MUXCTRL(V500_iocfg_reg49, 0x100C0088, PMX_GPIO2_5, PMX_SPI1_SDO) +MUXCTRL(V500_iocfg_reg50, 0x100C008C, PMX_GPIO2_6, PMX_SPI1_CSN0) +MUXCTRL(V500_iocfg_reg51, 0x100C0090, PMX_GPIO2_7, PMX_SPI1_SDI) +MUXCTRL(V500_iocfg_reg52, 0x100C0078, PMX_GPIO0_5, PMX_USB_OVRCUR) +MUXCTRL(V500_iocfg_reg53, 0x100C007C, PMX_GPIO0_6, PMX_USB_VBUS) +MUXCTRL(V500_iocfg_reg54, 0x100C0080, PMX_GPIO0_7, PMX_USB_PWREN) +MUXCTRL(V500_iocfg_reg55, 0x100C009C, PMX_GPIO9_0, PMX_PWM2) +MUXCTRL(V500_iocfg_reg56, 0x100C00A0, PMX_GPIO9_1, PMX_PWM3) +MUXCTRL(V500_iocfg_reg57, 0x100C00A4, PMX_GPIO2_3, PMX_SVB_PWM) +MUXCTRL(V500_iocfg_reg58, 0x100C0098, PMX_POR_SEL) +MUXCTRL(V500_iocfg_reg59, 0x100C0094, PMX_RST_N) +MUXCTRL(V500_iocfg_reg60, 0x100C0060, PMX_GPIO2_1, PMX_SFC_CLK, PMX_reserved, + PMX_reserved, PMX_SDIO1_CCLK_OUT) +MUXCTRL(V500_iocfg_reg61, 0x100C0064, PMX_GPIO2_2, PMX_SFC_WP_IO2, PMX_reserved, + PMX_reserved, PMX_SDIO1_CCMD) +MUXCTRL(V500_iocfg_reg62, 0x100C0068, PMX_GPIO3_0, PMX_SFC_MOSI_IO0, + PMX_reserved, PMX_reserved, PMX_SDIO1_CDATA0) +MUXCTRL(V500_iocfg_reg63, 0x100C006C, PMX_GPIO3_1, PMX_SFC_HOLD_IO3, + PMX_reserved, PMX_reserved, PMX_SDIO1_CDATA1) +MUXCTRL(V500_iocfg_reg64, 0x100C0070, PMX_GPIO3_2, PMX_SFC_CSN, PMX_reserved, + PMX_reserved, PMX_SDIO1_CDATA2) +MUXCTRL(V500_iocfg_reg65, 0x100C0074, PMX_GPIO3_3, PMX_SFC_MISO_IO1, + PMX_reserved, PMX_reserved, PMX_SDIO1_CDATA3) +MUXCTRL(V500_iocfg_reg66, 0x100C0030, PMX_GPIO3_4, PMX_reserved, PMX_reserved, + PMX_EMMC_DATA4) +MUXCTRL(V500_iocfg_reg67, 0x100C0034, PMX_GPIO3_5, PMX_reserved, PMX_reserved, + PMX_EMMC_DATA5) +MUXCTRL(V500_iocfg_reg68, 0x100C0038, PMX_GPIO3_6, PMX_reserved, PMX_reserved, + PMX_EMMC_DATA6) +MUXCTRL(V500_iocfg_reg69, 0x100C003C, PMX_GPIO3_7, PMX_reserved, PMX_reserved, + PMX_EMMC_DATA7) +MUXCTRL(V500_iocfg_reg70, 0x100C0040, PMX_GPIO4_0, PMX_SDIO0_CCLK_OUT, + PMX_JTAG_TCK, PMX_EMMC_CLK, PMX_SDIO1_CCLK_OUT, PMX_reserved, + PMX_reserved, PMX_SFC_INPUT_SEL) +MUXCTRL(V500_iocfg_reg71, 0x100C0044, PMX_GPIO4_1, PMX_SDIO0_CCMD, PMX_reserved, + PMX_EMMC_CMD, PMX_SDIO1_CCMD) +MUXCTRL(V500_iocfg_reg72, 0x100C0048, PMX_GPIO4_2, PMX_SDIO0_CDATA0, + PMX_JTAG_TMS, PMX_EMMC_DATA1, PMX_SDIO1_CDATA3) +MUXCTRL(V500_iocfg_reg73, 0x100C004C, PMX_GPIO4_3, PMX_SDIO0_CDATA1, + PMX_JTAG_TDO, PMX_EMMC_DATA2, PMX_SDIO1_CDATA2) +MUXCTRL(V500_iocfg_reg74, 0x100C0050, PMX_GPIO4_4, PMX_SDIO0_CDATA2, + PMX_JTAG_TDI, PMX_EMMC_DATA3, PMX_SDIO1_CDATA1) +MUXCTRL(V500_iocfg_reg75, 0x100C0054, PMX_GPIO4_5, PMX_SDIO0_CDATA3, + PMX_JTAG_TRSTN, PMX_EMMC_DATA0, PMX_SDIO1_CDATA0) +MUXCTRL(V500_iocfg_reg76, 0x100C0058, PMX_GPIO4_6, PMX_SDIO0_CARD_POWER_EN_N, + PMX_reserved, PMX_EMMC_DS) +MUXCTRL(V500_iocfg_reg77, 0x100C005C, PMX_GPIO4_7, PMX_SDIO0_CARD_DETECT, + PMX_reserved, PMX_EMMC_RST_N) +MUXCTRL(V500_iocfg_reg78, 0x100C001C, PMX_EMMC_DATA0, PMX_SFC_MISO_IO1) +MUXCTRL(V500_iocfg_reg79, 0x100C0020, PMX_EMMC_DATA3, PMX_SFC_WP_IO2) +MUXCTRL(V500_iocfg_reg80, 0x100C0028, PMX_EMMC_DATA1, PMX_SFC_CSN) +MUXCTRL(V500_iocfg_reg81, 0x100C0024, PMX_EMMC_DATA2, PMX_SFC_HOLD_IO3) +MUXCTRL(V500_iocfg_reg82, 0x100C0014, PMX_EMMC_CLK, PMX_SFC_CLK, + PMX_SFC_DEVICE_MODE) +MUXCTRL(V500_iocfg_reg83, 0x100C0018, PMX_EMMC_CMD, PMX_SFC_MOSI_IO0) +MUXCTRL(V500_iocfg_reg84, 0x100C002C, PMX_SYS_RSTN_OUT, PMX_WDG_RSTN, + PMX_SDIO0_CARD_POWER_EN_N, PMX_GPIO9_2) +MUXCTRL(V500_iocfg_reg85, 0x100C0000, PMX_GPIO0_1, PMX_UART0_RXD) +MUXCTRL(V500_iocfg_reg86, 0x100C0004, PMX_GPIO0_2, PMX_UART0_TXD, + PMX_FMC_STARTUP_DISABLE) +MUXCTRL(V500_iocfg_reg87, 0x100C0008, PMX_GPIO0_0, PMX_UPDATE_MODE, PMX_IR_IN) +MUXCTRL(V500_iocfg_reg88, 0x100C000C, PMX_GPIO0_3, PMX_PWM0, PMX_UART1_TXD, + PMX_I2C1_SCL) +MUXCTRL(V500_iocfg_reg89, 0x100C0010, PMX_GPIO0_4, PMX_PWM1, PMX_UART1_RXD, + PMX_I2C1_SDA) +MUXCTRL(V500_iocfg_reg90, 0x120C0010, PMX_JTAG_TRSTN, PMX_SPI1_CSN0, + PMX_GPIO1_4, PMX_reserved, PMX_UART2_RXD, PMX_I2S_MCLK) +MUXCTRL(V500_iocfg_reg91, 0x120C0014, PMX_JTAG_TCK, PMX_SPI1_SCLK, PMX_GPIO1_5, + PMX_reserved, PMX_UART2_TXD, PMX_I2S_BCLK) +MUXCTRL(V500_iocfg_reg92, 0x120C0018, PMX_JTAG_TMS, PMX_SPI1_SDI, PMX_GPIO1_6, + PMX_PWM2, PMX_UART2_CTSN, PMX_I2S_WS) +MUXCTRL(V500_iocfg_reg93, 0x120C001C, PMX_JTAG_TDO, PMX_SPI1_SDO, PMX_GPIO1_7, + PMX_reserved, PMX_UART2_RTSN, PMX_I2S_SD_RX) +MUXCTRL(V500_iocfg_reg94, 0x120C0020, PMX_JTAG_TDI, PMX_SPI1_CSN1, PMX_GPIO2_0, + PMX_SDIO0_CARD_POWER_EN_N, PMX_PWM3, PMX_I2S_SD_TX) +MUXCTRL(V500_iocfg_reg95, 0x120C0000, PMX_GPIO1_0, PMX_LSADC_CH0) +MUXCTRL(V500_iocfg_reg96, 0x120C0004, PMX_GPIO1_1, PMX_LSADC_CH1) +MUXCTRL(V500_iocfg_reg97, 0x120C0008, PMX_GPIO1_2, PMX_LSADC_CH2) +MUXCTRL(V500_iocfg_reg98, 0x120C000C, PMX_GPIO1_3, PMX_LSADC_CH3) + +static const muxctrl_reg_t *V500regs[] = { + &V500_iocfg_reg6, &V500_iocfg_reg7, + &V500_iocfg_reg8, &V500_iocfg_reg9, + &V500_iocfg_reg10, &V500_iocfg_reg11, + &V500_iocfg_reg12, &V500_iocfg_reg13, + &V500_iocfg_reg14, &V500_iocfg_reg15, + &V500_iocfg_reg16, &V500_iocfg_reg17, + &V500_iocfg_reg18, &V500_iocfg_reg19, + &V500_iocfg_reg20, &V500_iocfg_reg21, + &V500_iocfg_reg22, &V500_iocfg_reg23, + &V500_iocfg_reg24, &V500_iocfg_reg25, + &V500_iocfg_reg26, &V500_iocfg_reg27, + &V500_iocfg_reg28, &V500_iocfg_reg29, + &V500_iocfg_reg30, &V500_iocfg_reg31, + &V500_iocfg_reg32, &V500_iocfg_reg33, + &V500_iocfg_reg34, &V500_iocfg_reg35, + &V500_iocfg_reg36, &V500_iocfg_reg37, + &V500_iocfg_reg38, &V500_iocfg_reg39, + &V500_iocfg_reg40, &V500_iocfg_reg41, + &V500_iocfg_reg42, &V500_iocfg_reg43, + &V500_iocfg_reg44, &V500_iocfg_reg45, + &V500_iocfg_reg46, &V500_iocfg_reg47, + &V500_iocfg_reg48, &V500_iocfg_reg49, + &V500_iocfg_reg50, &V500_iocfg_reg51, + &V500_iocfg_reg52, &V500_iocfg_reg53, + &V500_iocfg_reg54, &V500_iocfg_reg55, + &V500_iocfg_reg56, &V500_iocfg_reg57, + &V500_iocfg_reg58, &V500_iocfg_reg59, + &V500_iocfg_reg60, &V500_iocfg_reg61, + &V500_iocfg_reg62, &V500_iocfg_reg63, + &V500_iocfg_reg64, &V500_iocfg_reg65, + &V500_iocfg_reg66, &V500_iocfg_reg67, + &V500_iocfg_reg68, &V500_iocfg_reg69, + &V500_iocfg_reg70, &V500_iocfg_reg71, + &V500_iocfg_reg72, &V500_iocfg_reg73, + &V500_iocfg_reg74, &V500_iocfg_reg75, + &V500_iocfg_reg76, &V500_iocfg_reg77, + &V500_iocfg_reg78, &V500_iocfg_reg79, + &V500_iocfg_reg80, &V500_iocfg_reg81, + &V500_iocfg_reg82, &V500_iocfg_reg83, + &V500_iocfg_reg84, &V500_iocfg_reg85, + &V500_iocfg_reg86, &V500_iocfg_reg87, + &V500_iocfg_reg88, &V500_iocfg_reg89, + &V500_iocfg_reg90, &V500_iocfg_reg91, + &V500_iocfg_reg92, &V500_iocfg_reg93, + &V500_iocfg_reg94, &V500_iocfg_reg95, + &V500_iocfg_reg96, &V500_iocfg_reg97, + &V500_iocfg_reg98, 0, +}; + #endif /* IPCHW_PADMUX_V4 */ #if defined(IPCHW_PADMUX_3536D) /* hi3536dv100 */ @@ -2875,7 +3098,7 @@ static const muxctrl_reg_t **regs_by_chip() { else if (IS_16DV200) return DV200regs; else if (IS_7205V500) - return EV200regs; + return V500regs; break; #endif #ifdef IPCHW_PADMUX_V5 diff --git a/src/reginfo_test.c b/src/reginfo_test.c index bfd37520..b8927417 100644 --- a/src/reginfo_test.c +++ b/src/reginfo_test.c @@ -240,6 +240,43 @@ static void test_v4_pwm(void) { } #endif +#ifdef IPCHW_PADMUX_V4 +static void test_v500_pwm(void) { + puts("V4 (gk7205v510): twelve PWM channels, its own pad table"); + as_chip(HISI_V4, "7205V510"); + + /* The IR lamps of the Zenointel SD-2N-4G: PWM8 on GPIO7_0 at selector 5 + * and PWM9 on GPIO6_7 at selector 2, per XMedia's PIN_OUT_V510 and the + * stock firmware's own pwm.ko. These chips used to get the ev200 table, + * which calls the first of those pads LCD_DATA4 and knows no PWM8. */ + ipchw_padmux_t r; + if (one("PWM8", &r)) { + CHECK(r.address == 0x112C0058); + CHECK(r.func == 5); + CHECK(r.gpio_pad == 56); + } + if (one("PWM9", &r)) { + CHECK(r.address == 0x112C0068); + CHECK(r.func == 2); + CHECK(r.gpio_pad == 55); + } + if (one("PWM11", &r)) { + CHECK(r.address == 0x112C0074); + CHECK(r.func == 5); + } + + ipchw_padmux_t rows[8]; + int n = ipchw_padmux_by_pad(56, rows, 8); + CHECK(n >= 2); + for (int i = 0; i < n && i < 8; i++) + CHECK(strcmp(rows[i].func_name, "LCD_DATA4") != 0); + + /* The core-voltage PWM is its own pad and its own function name, so a + * PWMn lookup can never land on it. */ + CHECK(ipchw_padmux_by_func("SVB_PWM", rows, 8) == 1); +} +#endif + #ifdef IPCHW_PADMUX_V1 static void test_prefix_is_not_substring(void) { puts("a PWM prefix must not catch SVB_PWM"); @@ -1013,6 +1050,7 @@ static void test_table_integrity(void) { {HISI_V4, "3516EV300"}, {HISI_V4, "3518EV300"}, {HISI_V4, "3516DV200"}, + {HISI_V4, "7205V510"}, {HISI_V4A, "3516CV500"}, {HISI_V4A, "3516AV300"}, {HISI_OT, "3516CV610"}, @@ -1159,6 +1197,7 @@ int main(void) { #endif #ifdef IPCHW_PADMUX_V4 test_v4_pwm(); + test_v500_pwm(); test_counts_past_max(); test_get_set(); #endif From 051bd01bdc535d484db17c097a02fd84b3ae1cc0 Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com> Date: Sun, 4 Oct 2026 20:36:21 +0300 Subject: [PATCH 2/3] hisi: FMC_STARTUP_DISABLE on UART0_TXD for gk7205v530 only The V500 table carried the selector the V530 pin-out adds to UART0_TXD for all three chips, so on a V500 or V510 a caller could find FMC_STARTUP_DISABLE and have ipchw_padmux_set() write selector 2 to the console's TX pad, a value the V510 sheet does not list. V530regs now differs from V500regs in that one row, picked by chip name; the other rows stay shared through two macros rather than a second copy of the list. reginfo_test: a 7205V510 offers no FMC_STARTUP_DISABLE, a 7205V530 offers it at selector 2 and still resolves PWM8, and V530 joins the integrity sweep. --- src/reginfo.c | 106 ++++++++++++++++++++++----------------------- src/reginfo_test.c | 13 ++++++ 2 files changed, 66 insertions(+), 53 deletions(-) diff --git a/src/reginfo.c b/src/reginfo.c index 49812143..2c817d2a 100644 --- a/src/reginfo.c +++ b/src/reginfo.c @@ -2115,11 +2115,13 @@ static const muxctrl_reg_t *DV200regs[] = { /* GK7205V500 / V510 / V530 (XMedia XM720xxx). Not an ev200: the pads sit at * the same iocfg addresses but behind different selectors, and the block has * twelve PWM channels, not four. Generated from XMedia's PIN_OUT_V510.xlsx - * (sheet 1, "Function Number" per pin; addresses from sheet 3), plus the one - * selector PIN_OUT_V530.xlsx adds (FMC_STARTUP_DISABLE on UART0_TXD). The two - * workbooks agree on every other row; the QFN V330/V230 pin-outs are strict - * subsets of it. iocfg_reg0-5 are the power-sequencing pins, which have no - * selector. */ + * (sheet 1, "Function Number" per pin; addresses from sheet 3). The V530 + * workbook agrees on every row but UART0_TXD, where it adds selector 2, + * FMC_STARTUP_DISABLE: that row is the one thing V530regs does not share, + * because the V510 sheet does not list the selector and a table that offered + * it there would let a caller write an undocumented value to the console's + * TX pad. The QFN V330/V230 pin-outs are strict subsets of V510. + * iocfg_reg0-5 are the power-sequencing pins, which have no selector. */ MUXCTRL(V500_iocfg_reg6, 0x112C0074, PMX_GPIO6_4, PMX_reserved, PMX_UART1_TXD, PMX_I2C1_SCL, PMX_reserved, PMX_PWM11, PMX_reserved, PMX_SPI0_SCLK) MUXCTRL(V500_iocfg_reg7, 0x112C0070, PMX_GPIO6_5, PMX_VI_BT1120_DATA2, @@ -2262,7 +2264,8 @@ MUXCTRL(V500_iocfg_reg83, 0x100C0018, PMX_EMMC_CMD, PMX_SFC_MOSI_IO0) MUXCTRL(V500_iocfg_reg84, 0x100C002C, PMX_SYS_RSTN_OUT, PMX_WDG_RSTN, PMX_SDIO0_CARD_POWER_EN_N, PMX_GPIO9_2) MUXCTRL(V500_iocfg_reg85, 0x100C0000, PMX_GPIO0_1, PMX_UART0_RXD) -MUXCTRL(V500_iocfg_reg86, 0x100C0004, PMX_GPIO0_2, PMX_UART0_TXD, +MUXCTRL(V500_iocfg_reg86, 0x100C0004, PMX_GPIO0_2, PMX_UART0_TXD) +MUXCTRL(V530_iocfg_reg86, 0x100C0004, PMX_GPIO0_2, PMX_UART0_TXD, PMX_FMC_STARTUP_DISABLE) MUXCTRL(V500_iocfg_reg87, 0x100C0008, PMX_GPIO0_0, PMX_UPDATE_MODE, PMX_IR_IN) MUXCTRL(V500_iocfg_reg88, 0x100C000C, PMX_GPIO0_3, PMX_PWM0, PMX_UART1_TXD, @@ -2284,54 +2287,49 @@ MUXCTRL(V500_iocfg_reg96, 0x120C0004, PMX_GPIO1_1, PMX_LSADC_CH1) MUXCTRL(V500_iocfg_reg97, 0x120C0008, PMX_GPIO1_2, PMX_LSADC_CH2) MUXCTRL(V500_iocfg_reg98, 0x120C000C, PMX_GPIO1_3, PMX_LSADC_CH3) +#define V500_REGS_HEAD \ + &V500_iocfg_reg6, &V500_iocfg_reg7, &V500_iocfg_reg8, &V500_iocfg_reg9, \ + &V500_iocfg_reg10, &V500_iocfg_reg11, &V500_iocfg_reg12, \ + &V500_iocfg_reg13, &V500_iocfg_reg14, &V500_iocfg_reg15, \ + &V500_iocfg_reg16, &V500_iocfg_reg17, &V500_iocfg_reg18, \ + &V500_iocfg_reg19, &V500_iocfg_reg20, &V500_iocfg_reg21, \ + &V500_iocfg_reg22, &V500_iocfg_reg23, &V500_iocfg_reg24, \ + &V500_iocfg_reg25, &V500_iocfg_reg26, &V500_iocfg_reg27, \ + &V500_iocfg_reg28, &V500_iocfg_reg29, &V500_iocfg_reg30, \ + &V500_iocfg_reg31, &V500_iocfg_reg32, &V500_iocfg_reg33, \ + &V500_iocfg_reg34, &V500_iocfg_reg35, &V500_iocfg_reg36, \ + &V500_iocfg_reg37, &V500_iocfg_reg38, &V500_iocfg_reg39, \ + &V500_iocfg_reg40, &V500_iocfg_reg41, &V500_iocfg_reg42, \ + &V500_iocfg_reg43, &V500_iocfg_reg44, &V500_iocfg_reg45, \ + &V500_iocfg_reg46, &V500_iocfg_reg47, &V500_iocfg_reg48, \ + &V500_iocfg_reg49, &V500_iocfg_reg50, &V500_iocfg_reg51, \ + &V500_iocfg_reg52, &V500_iocfg_reg53, &V500_iocfg_reg54, \ + &V500_iocfg_reg55, &V500_iocfg_reg56, &V500_iocfg_reg57, \ + &V500_iocfg_reg58, &V500_iocfg_reg59, &V500_iocfg_reg60, \ + &V500_iocfg_reg61, &V500_iocfg_reg62, &V500_iocfg_reg63, \ + &V500_iocfg_reg64, &V500_iocfg_reg65, &V500_iocfg_reg66, \ + &V500_iocfg_reg67, &V500_iocfg_reg68, &V500_iocfg_reg69, \ + &V500_iocfg_reg70, &V500_iocfg_reg71, &V500_iocfg_reg72, \ + &V500_iocfg_reg73, &V500_iocfg_reg74, &V500_iocfg_reg75, \ + &V500_iocfg_reg76, &V500_iocfg_reg77, &V500_iocfg_reg78, \ + &V500_iocfg_reg79, &V500_iocfg_reg80, &V500_iocfg_reg81, \ + &V500_iocfg_reg82, &V500_iocfg_reg83, &V500_iocfg_reg84, \ + &V500_iocfg_reg85, + +#define V500_REGS_TAIL \ + &V500_iocfg_reg87, &V500_iocfg_reg88, &V500_iocfg_reg89, \ + &V500_iocfg_reg90, &V500_iocfg_reg91, &V500_iocfg_reg92, \ + &V500_iocfg_reg93, &V500_iocfg_reg94, &V500_iocfg_reg95, \ + &V500_iocfg_reg96, &V500_iocfg_reg97, &V500_iocfg_reg98, + static const muxctrl_reg_t *V500regs[] = { - &V500_iocfg_reg6, &V500_iocfg_reg7, - &V500_iocfg_reg8, &V500_iocfg_reg9, - &V500_iocfg_reg10, &V500_iocfg_reg11, - &V500_iocfg_reg12, &V500_iocfg_reg13, - &V500_iocfg_reg14, &V500_iocfg_reg15, - &V500_iocfg_reg16, &V500_iocfg_reg17, - &V500_iocfg_reg18, &V500_iocfg_reg19, - &V500_iocfg_reg20, &V500_iocfg_reg21, - &V500_iocfg_reg22, &V500_iocfg_reg23, - &V500_iocfg_reg24, &V500_iocfg_reg25, - &V500_iocfg_reg26, &V500_iocfg_reg27, - &V500_iocfg_reg28, &V500_iocfg_reg29, - &V500_iocfg_reg30, &V500_iocfg_reg31, - &V500_iocfg_reg32, &V500_iocfg_reg33, - &V500_iocfg_reg34, &V500_iocfg_reg35, - &V500_iocfg_reg36, &V500_iocfg_reg37, - &V500_iocfg_reg38, &V500_iocfg_reg39, - &V500_iocfg_reg40, &V500_iocfg_reg41, - &V500_iocfg_reg42, &V500_iocfg_reg43, - &V500_iocfg_reg44, &V500_iocfg_reg45, - &V500_iocfg_reg46, &V500_iocfg_reg47, - &V500_iocfg_reg48, &V500_iocfg_reg49, - &V500_iocfg_reg50, &V500_iocfg_reg51, - &V500_iocfg_reg52, &V500_iocfg_reg53, - &V500_iocfg_reg54, &V500_iocfg_reg55, - &V500_iocfg_reg56, &V500_iocfg_reg57, - &V500_iocfg_reg58, &V500_iocfg_reg59, - &V500_iocfg_reg60, &V500_iocfg_reg61, - &V500_iocfg_reg62, &V500_iocfg_reg63, - &V500_iocfg_reg64, &V500_iocfg_reg65, - &V500_iocfg_reg66, &V500_iocfg_reg67, - &V500_iocfg_reg68, &V500_iocfg_reg69, - &V500_iocfg_reg70, &V500_iocfg_reg71, - &V500_iocfg_reg72, &V500_iocfg_reg73, - &V500_iocfg_reg74, &V500_iocfg_reg75, - &V500_iocfg_reg76, &V500_iocfg_reg77, - &V500_iocfg_reg78, &V500_iocfg_reg79, - &V500_iocfg_reg80, &V500_iocfg_reg81, - &V500_iocfg_reg82, &V500_iocfg_reg83, - &V500_iocfg_reg84, &V500_iocfg_reg85, - &V500_iocfg_reg86, &V500_iocfg_reg87, - &V500_iocfg_reg88, &V500_iocfg_reg89, - &V500_iocfg_reg90, &V500_iocfg_reg91, - &V500_iocfg_reg92, &V500_iocfg_reg93, - &V500_iocfg_reg94, &V500_iocfg_reg95, - &V500_iocfg_reg96, &V500_iocfg_reg97, - &V500_iocfg_reg98, 0, + V500_REGS_HEAD & V500_iocfg_reg86, + V500_REGS_TAIL 0, +}; + +static const muxctrl_reg_t *V530regs[] = { + V500_REGS_HEAD & V530_iocfg_reg86, + V500_REGS_TAIL 0, }; #endif /* IPCHW_PADMUX_V4 */ @@ -3097,6 +3095,8 @@ static const muxctrl_reg_t **regs_by_chip() { return _8EV300regs; else if (IS_16DV200) return DV200regs; + else if (IS_CHIP("7205V530")) + return V530regs; else if (IS_7205V500) return V500regs; break; diff --git a/src/reginfo_test.c b/src/reginfo_test.c index b8927417..2ee97256 100644 --- a/src/reginfo_test.c +++ b/src/reginfo_test.c @@ -274,6 +274,18 @@ static void test_v500_pwm(void) { /* The core-voltage PWM is its own pad and its own function name, so a * PWMn lookup can never land on it. */ CHECK(ipchw_padmux_by_func("SVB_PWM", rows, 8) == 1); + + /* FMC_STARTUP_DISABLE on UART0_TXD is in the V530 pin-out only. Offering + * it on a V510 would let a caller write a selector its sheet does not + * list to the console's TX pad. */ + CHECK(ipchw_padmux_by_func("FMC_STARTUP_DISABLE", rows, 8) == 0); + as_chip(HISI_V4, "7205V530"); + if (one("FMC_STARTUP_DISABLE", &r)) { + CHECK(r.address == 0x100C0004); + CHECK(r.func == 2); + } + if (one("PWM8", &r)) + CHECK(r.address == 0x112C0058 && r.func == 5); } #endif @@ -1051,6 +1063,7 @@ static void test_table_integrity(void) { {HISI_V4, "3518EV300"}, {HISI_V4, "3516DV200"}, {HISI_V4, "7205V510"}, + {HISI_V4, "7205V530"}, {HISI_V4A, "3516CV500"}, {HISI_V4A, "3516AV300"}, {HISI_OT, "3516CV610"}, From c2862e2b75fdc84332bdf405abff757ece1f6052 Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com> Date: Sun, 4 Oct 2026 20:36:49 +0300 Subject: [PATCH 3/3] hisi: keep the V500/V530 list commas outside the shared macros clang-format read the trailing comma inside V500_REGS_HEAD as an expression and rendered the next element as "V500_REGS_HEAD & V500_iocfg_reg86", which compiles to the right thing and reads as a bitwise AND. --- src/reginfo.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/reginfo.c b/src/reginfo.c index 2c817d2a..f16e3c39 100644 --- a/src/reginfo.c +++ b/src/reginfo.c @@ -2314,22 +2314,26 @@ MUXCTRL(V500_iocfg_reg98, 0x120C000C, PMX_GPIO1_3, PMX_LSADC_CH3) &V500_iocfg_reg76, &V500_iocfg_reg77, &V500_iocfg_reg78, \ &V500_iocfg_reg79, &V500_iocfg_reg80, &V500_iocfg_reg81, \ &V500_iocfg_reg82, &V500_iocfg_reg83, &V500_iocfg_reg84, \ - &V500_iocfg_reg85, + &V500_iocfg_reg85 #define V500_REGS_TAIL \ &V500_iocfg_reg87, &V500_iocfg_reg88, &V500_iocfg_reg89, \ &V500_iocfg_reg90, &V500_iocfg_reg91, &V500_iocfg_reg92, \ &V500_iocfg_reg93, &V500_iocfg_reg94, &V500_iocfg_reg95, \ - &V500_iocfg_reg96, &V500_iocfg_reg97, &V500_iocfg_reg98, + &V500_iocfg_reg96, &V500_iocfg_reg97, &V500_iocfg_reg98 static const muxctrl_reg_t *V500regs[] = { - V500_REGS_HEAD & V500_iocfg_reg86, - V500_REGS_TAIL 0, + V500_REGS_HEAD, + &V500_iocfg_reg86, + V500_REGS_TAIL, + 0, }; static const muxctrl_reg_t *V530regs[] = { - V500_REGS_HEAD & V530_iocfg_reg86, - V500_REGS_TAIL 0, + V500_REGS_HEAD, + &V530_iocfg_reg86, + V500_REGS_TAIL, + 0, }; #endif /* IPCHW_PADMUX_V4 */