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add the new entry to the ISA.json under the "extensions" section #21

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@yskzalloc

Is it possible to add the following extensions in ISA.json?
I wonder if there is any prioritized work for this issue. It is a table of added extensions in this link.

Specification name Ratification date New extension(s) or Profile(s)
RISC-V Quality-of-Service (QoS) Identifiers Jun-24 Ssqosid
Obviating Memory-Management Instructions after Marking PTEs Valid Jun-24 Svvptc
Resumable Non-Maskable Interrupts Jun-24 Smrnmi
Shadow Stacks and Landing Pads Jun-24 Zicfiss, Zicfilp
BF16 Extensions Jun-24 Zfbfmin, Zvfbfmin, Zvfbfwma
Zaamo and Zalrsc Extensions Apr-24 Zaamo, Zalrsc
B Standard Extension for Bit Manipulation Instructions Apr-24 B
Byte and Halfword Atomic Memory Operations (Zabha) Apr-24 Zabha
RISC-V Supervisor Counter Delegation Mar-24 Smcdeleg, Ssccfg
May-Be-Operations Mar-24 Zimop, Zcmop
RISC-V Indirect CSR Access (Smcsrind/Sscsrind) Feb-24 Smcsrind, Sscsrind
RISC-V Integer Conditional (Zicond) operations extension Nov-23 Zicond
Hardware Updating of PTE A/D Bits (Svadu) Nov-23 Svadu
RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf) Nov-23 Smcntrpmf
Atomic Compare-and-Swap (CAS) Instructions (Zacas) Nov-23 Zacas
RISC-V Cryptography Extensions Volume II: Vector Instructions Sep-23 Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt
"Zfa" Standard Extension for Additional Floating-Point Instructions Sep-23 Zfa
RISC-V Advanced Interrupt Architecture Jun-23 Smaia, Ssaia
“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half- Jun-23 Zvfh, Zvfhmin
Precision Floating-Point Arithmetic
“Zihintntl” Non-Temporal Locality Hints May-23 Zihintntl
RISC-V Code Size Reduction Apr-23 Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt
RISC-V Profiles Mar-23 RVA20, RVI20, RVA22
"Zicntr" and "Zihpm" Counters Mar-23 Zicntr, Zihpm
RV32E and RV64E Base Integer Instruction Sets Jan-23 RV32E/RV64E
“Ztso” Standard Extension for Total Store Ordering Jan-23 Ztso
RISC-V Wait-on-Reservation-Set (Zawrs) extension Nov-22 Zawrs
Zmmul Extension Jun-22 Zmmul
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) Nov-21 Smepmp
RISC-V Base Cache Management Operation ISA Extensions Nov-21 Zicbom, Zicbop, Zicboz
RISC-V Bit-Manipulation ISA-extensions Nov-21 Zba, Zbb, Zbc, Zbs
RISC-V Count Overflow and Mode-Based Filtering Extension Nov-21 Sscofpmf
RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions Nov-21 Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr
RISC-V State Enable Extension Nov-21 Smstateen
RISC-V "stimecmp / vstimecmp" Extension Nov-21 Sstc
RISC-V Vector Extension Nov-21 Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv
The RISC-V Instruction Set Manual Volume II: Privileged Architecture Nov-21 Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt
"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point Nov-21 Zfh, Zfhmin
"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers Nov-21 Zfinx, Zdinx, Zhinx, Zhinxmin
“Zihintpause” Pause Hint Feb-21 Zihintpause
The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Dec-19 A, D, F, RV32I, RV64I, Zaamo, Zalrsc, Zicsr, Zifencei
The RISC-V Instruction Set Manual Volume II: Privileged Architecture Dec-19 C, M, Q, Sm1p11, Ss1p11, Sv32, Sv39, Sv48

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