[Bug] corner case bug in Vfdsu floating point DivSqrt

[ashraf629]

This bug was found using formal methods.

If Vfdsu receives a new instruction and finishes stage EX1 at the same time stage EX2 finishes for a previous instruction (so that the ex1_pipedown and ex2_pipedown wires in the control module are high at the same time), total_qt_rt in the srt module is set to 0, and the EX3 stage reads this 0 resulting in an incorrect result.

Suggested fix:

In ct_vfdsu_srt.v, change total_qt_rt_58 from a wire into a register. Change all instances of total_qt_rt into total_qt_rt_next. Change the register update logic in lines 525 to 611 to include total_qt_rt_58:

always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    // rest of code
    total_qt_rt_58            <= '0;
  end
  else if(ex2_pipedown)
  begin
    // rest of code
    total_qt_rt_58            <= total_qt_rt_next;
  end
  else
  begin
    // rest_of_code
    total_qt_rt_58            <= total_qt_rt_58;
  end
end

, and remove the assignment on line 750: assign total_qt_rt_58[57:0] = {total_qt_rt[57:2],2'b00};.

In ct_vfdsu_srt_radix16_with_sqrt.v, change total_qt_rt in lines 35 and 57 to total_qt_rt_next.