Passthrough Stream Fifo Correct Specification

[arj4web]

Hi,

I was seeing the code of the passthrough stream FIFO, which intends to allow write when read and write are to happen in the same cycle. But in the code, I observe that only assertions are used to stop the FIFO from being pushed when full or popped when empty. Is this somewhat expected behaviour/specification?

Or was the intention to block till we receive a pop/read request and vice-versa?

[phsauter]

I am not quite sure what the intention was, @thommythomaso do you remember?
In my opinion gating the update of the pointers would probably be a good idea since it should cost only very few gates at most. However, this would change the behavior of the current implementation iff people turn off the asserts or just never run a RTL simulation.

I am inclined to saying the assertions are there to enforce a contract and if you violate this contract, we do not guarantee equivalence. (ie you are holding it wrong)
@niwis Opinions? Is this a request for v2 or could this be done before?

[TheMightyDuckOfDoom]

@phsauter I wrote it for the Multiprotocol-IDMA project.
And yes, I think it would be a very good idea to check for the handshake.

Currently we assume that:

• We only ever receive a ready_i if valid_o is asserted
• We only ever receive a valid_i if ready_o is asserted

The assertions are there to check this during simulations, but obviously this gets lost if assertions are turned off or a synthesized netlist is used.

But as far as I remember there was no intentional reason or requirement for this behavior.