diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index e2baf5cf..a58ab117 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -126,11 +126,11 @@ jobs:
           cargo install svd2rust --path .
 
       # Install the MSRV toolchain
-      - uses: dtolnay/rust-toolchain@1.81.0
+      - uses: dtolnay/rust-toolchain@1.85.0
       - name: Run reression tool with MSRV
         # The MSRV only applies to the generated crate. The regress tool should still be run with
         # stable.
-        run: cargo +stable regress tests --toolchain 1.81.0 -m Nordic -- --strict --atomics
+        run: cargo +stable regress tests --toolchain 1.85.0 -m Nordic -- --strict --atomics
 
   ci-docs-clippy:
     runs-on: ubuntu-latest
diff --git a/CHANGELOG.md b/CHANGELOG.md
index de19fa9b..51e15f97 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 - Add AVR specific settings (`avr_config`) to the `--settings` file, declaring
   which registers are CCP protected; `Protected` trait implementations are
   generated from it
+- Add `Reg::prepare`.
 
 ## [v0.37.1] - 2025-10-17
 
diff --git a/README.md b/README.md
index 830e1f67..752d9584 100644
--- a/README.md
+++ b/README.md
@@ -17,9 +17,9 @@ This project is developed and maintained by the [Tools team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-The **generated code** is guaranteed to compile on stable Rust 1.81.0 and up.
+The **generated code** is guaranteed to compile on stable Rust 1.85.0 and up.
 
-If you encounter compilation errors on any stable version newer than 1.81.0, please open an issue.
+If you encounter compilation errors on any stable version newer than 1.85.0, please open an issue.
 
 # Testing Locally
 
diff --git a/src/generate/generic_reg_vcell.rs b/src/generate/generic_reg_vcell.rs
index 9e436334..2dd3aeeb 100644
--- a/src/generate/generic_reg_vcell.rs
+++ b/src/generate/generic_reg_vcell.rs
@@ -88,6 +88,20 @@ impl<REG: Resettable + Writable> Reg<REG> {
         value
     }
 
+    /// Prepare bits for delayed write to register.
+    #[inline(always)]
+    pub fn prepare<F>(&self, f: F) -> REG::Ux
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits
+    }
+
     /// Writes bits to a `Writable` register and produce a value.
     ///
     /// You can write raw bits into a register: