feat(asic): Intel BZM2 (Bonanza Mine 2) ASIC family support#69
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feat(asic): Intel BZM2 (Bonanza Mine 2) ASIC family support#69recklessnode wants to merge 2 commits into
recklessnode wants to merge 2 commits into
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…d telemetry types
Infrastructure groundwork usable by any board, no new dependencies:
- Wire the per-board command channel end to end: BackplaneConnector and
api::registry::BoardRegistration gain an optional
mpsc::Sender<BoardCommand>; the backplane forwards it at start_board.
BoardCommand::SetFanTarget and SetFanTargetRequest existed but nothing
wired them - PATCH /api/v0/boards/{name}/fans/{fan} now drives them
(boards opt in by populating command_tx; all current boards answer
"accepts no commands" until they grow a command loop).
- BoardRegistry::board(name) + command_tx(name) accessors with lazy
disconnect pruning; get_board refactored onto the former.
- board/power.rs: PowerRail trait (Tps546PowerRail, FilePowerRail file
adapters, FileGpioPin) + GpioResetLine (AsicEnable impl) +
VoltageStackBringupPlan for ordered multi-rail bring-up with settle
delays and reverse-order shutdown.
- hash_thread: HashThreadTemperatureReading/PowerReading/
TelemetryUpdate + HashThreadEvent::TelemetryUpdate (typed path for
thread-sourced sensor data; bitaxe's monitor TODO wants this) and
HashThreadError as a shared thread error vocabulary.
- Backplane::attach_configured_board: attach an env-configured virtual
board without synthesizing a transport event.
- BoardTelemetry.asics (serde-default) + AsicState/EngineCoordinate:
generic per-ASIC topology/diagnostics state for multi-ASIC boards.
- transport/serial: Clone derives on the Arc-backed reader/writer/
control halves.
- .gitattributes for LF normalization.
The protocol/transport layer for the Intel BZM2 mining ASIC, mirroring the bm13xx in-tree structure (protocol codec / controller / thread): - protocol.rs: pure codec - opcodes, frame encoders (write_job, write_register, noop, loopback, read_result), TDM frame/result parsers, the 20x12 logical engine grid (default 236 active engines), target -> leading-zeros conversion. Deps: bitcoin + std only. - uart.rs: Bzm2UartController over the 9-bit multidrop UART - register R/W (unicast/multicast/local), NOOP "BZ2" verification, chain enumeration (ID-assignment walk from the 0xFA default), TDM enable/sync reads, engine-map discovery, loopback, DTS/VS sensor configure + query. - clock.rs: Bzm2ClockController - PLL/DLL program/enable/lock-wait (per-ASIC and broadcast), clock debug reports. - thread.rs: Bzm2Thread implementing HashThread - direct UART work dispatch, TDM result handling with per-ASIC/per-PLL hashrate estimation, DTS/VS telemetry via HashThreadEvent::TelemetryUpdate, thermal-trip frame handling, diagnostic command handle. Tests are PTY-based chain emulations, gated #[cfg(all(test, unix))] so non-Unix hosts still build the crate cleanly.
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This was referenced Jun 11, 2026
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Part 2 of the BZM2 series (stacked on part 1 — review the
feat(asic)commit). Adds the ASIC-family layer for the Intel BZM2 (Bonanza Mine 2), the chip the 256 Foundation received as a 54,000-unit grant and that the Satoshi Starter / bitaxeBIRDS board family is built around.The layout mirrors the in-tree
bm13xxstructure (pure codec → controller →HashThread):protocol.rs— opcodes, frame encoders (write_job,write_register,noop,loopback,read_result), TDM frame/result parsers, the 20×12 logical engine grid (236 active engines by default), target→leading-zeros conversion. Depends onbitcoin+ std only.uart.rs—Bzm2UartControllerfor the chip's 9-bit multidrop UART: register R/W (unicast/multicast/local), NOOP"BZ2"verification, chain enumeration (ID-assignment walk from the0xFApower-on default), TDM enable and synchronized reads, engine-map discovery, loopback, and DTS/VS (on-die temperature/voltage sensor) configure + query.clock.rs—Bzm2ClockController: PLL/DLL program/enable/lock-wait, per-ASIC and broadcast, plus clock debug reports.thread.rs—Bzm2ThreadimplementingHashThread: direct UART work dispatch, TDM result handling with per-ASIC/per-PLL hashrate estimation, DTS/VS telemetry emitted viaHashThreadEvent::TelemetryUpdate(from part 1), thermal-trip frame handling, and a diagnostics handle used by the board layer in part 3.Unlike the BM13xx family, the BZM2 is publicly documented — the protocol reference and integration guide land with part 4 (CC-BY-SA), so this driver can be reviewed against the chip's actual documentation rather than reverse engineering.
Tests are PTY-based chain emulations (multi-ASIC enumeration, TDM result paths, DTS/VS frames), gated
#[cfg(all(test, unix))]so non-Unix hosts build the crate cleanly.Gates:
cargo build(0 warnings),cargo test(362 passed / 0 failed),cargo fmtclean.🤖 Generated with Claude Code