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12 changes: 6 additions & 6 deletions edg/abstract_parts/AnalogSwitch.py
Original file line number Diff line number Diff line change
Expand Up @@ -130,8 +130,8 @@ def __init__(self) -> None:
self.inputs = self.Port(Vector(AnalogSink.empty()))
self.out = self.Port(
AnalogSource(
voltage_out=self.inputs.hull(lambda x: x.link().voltage),
signal_out=self.inputs.hull(lambda x: x.link().signal),
voltage=self.inputs.hull(lambda x: x.link().voltage),
signal=self.inputs.hull(lambda x: x.link().signal),
current_limits=self.device.analog_current_limits, # this device only, current draw propagated
impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance),
)
Expand All @@ -150,7 +150,7 @@ def generate(self) -> None:
input = self.inputs.append_elt(
AnalogSink(
voltage_limits=self.device.analog_voltage_limits, # this device only, voltages propagated
current_draw=self.out.link().current_drawn,
current_draw=self.out.link().current_draw,
impedance=self.out.link().sink_impedance + self.device.analog_on_resistance,
),
elt,
Expand Down Expand Up @@ -184,7 +184,7 @@ def __init__(self) -> None:
self.input = self.Port(
AnalogSink(
voltage_limits=self.device.analog_voltage_limits, # this device only, voltages propagated
current_draw=self.outputs.hull(lambda x: x.link().current_drawn),
current_draw=self.outputs.hull(lambda x: x.link().current_draw),
impedance=self.device.analog_on_resistance + self.outputs.hull(lambda x: x.link().sink_impedance),
)
)
Expand All @@ -201,8 +201,8 @@ def generate(self) -> None:
for elt in self.get(self.outputs.requested()):
output = self.outputs.append_elt(
AnalogSource(
voltage_out=self.input.link().voltage,
signal_out=self.input.link().signal,
voltage=self.input.link().voltage,
signal=self.input.link().signal,
current_limits=self.device.analog_current_limits, # this device only, voltages propagated
impedance=self.input.link().source_impedance + self.device.analog_on_resistance,
),
Expand Down
2 changes: 1 addition & 1 deletion edg/abstract_parts/Battery.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,6 @@ def __init__(self, voltage: RangeLike, current: RangeLike = RangeExpr.ZERO, *, c
self.capacity = self.ArgParameter(capacity)
self.actual_capacity = self.Parameter(RangeExpr())

self.require(self.pwr.voltage_out.within(voltage + self.gnd.link().voltage))
self.require(self.pwr.voltage.within(voltage + self.gnd.link().voltage))
self.require(self.pwr.current_limits.contains(current))
self.require(self.actual_capacity.upper() >= capacity)
6 changes: 3 additions & 3 deletions edg/abstract_parts/Capacitor.py
Original file line number Diff line number Diff line change
Expand Up @@ -450,7 +450,7 @@ def __init__(self, capacitance: RangeLike, output_bias: RangeLike, *, exact_capa

self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input])
self.output = self.Port(
AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr(), impedance=self.input.link().source_impedance),
AnalogSource(voltage=RangeExpr(), signal=RangeExpr(), impedance=self.input.link().source_impedance),
[Output],
)

Expand All @@ -472,12 +472,12 @@ def contents(self) -> None:
self.assign(self.input.impedance, self.output.link().sink_impedance) # assumed high frequency
voltage_halfspan = (self.input.link().voltage.upper() - self.input.link().voltage.lower()) / 2
self.assign(
self.output.voltage_out,
self.output.voltage,
(self.output_bias.lower() - voltage_halfspan, self.output_bias.upper() + voltage_halfspan),
)
signal_halfspan = (self.input.link().signal.upper() - self.input.link().signal.lower()) / 2
self.assign(
self.output.signal_out,
self.output.signal,
(self.output_bias.lower() - signal_halfspan, self.output_bias.upper() + signal_halfspan),
)

Expand Down
6 changes: 3 additions & 3 deletions edg/abstract_parts/FerriteBead.py
Original file line number Diff line number Diff line change
Expand Up @@ -119,22 +119,22 @@ def __init__(self, hf_impedance: RangeLike = RangeExpr.ALL, dc_resistance: Range
self.pwr_in = self.Port(VoltageSink(voltage_limits=Range.all(), current_draw=RangeExpr()), [Power, Input])
self.pwr_out = self.Port(
VoltageSource(
voltage_out=self.pwr_in.link().voltage, # ignore voltage drop
voltage=self.pwr_in.link().voltage, # ignore voltage drop
current_limits=RangeExpr(),
),
[Output],
)

self.fb = self.Block(
FerriteBead(
current=self.pwr_out.link().current_drawn, hf_impedance=hf_impedance, dc_resistance=dc_resistance
current=self.pwr_out.link().current_draw, hf_impedance=hf_impedance, dc_resistance=dc_resistance
)
)

self.connect(self.pwr_in.net, self.fb.a)
self.connect(self.pwr_out.net, self.fb.b)

self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw)
self.assign(self.pwr_out.current_limits, self.fb.actual_current_rating)

def connected(
Expand Down
6 changes: 3 additions & 3 deletions edg/abstract_parts/Fuse.py
Original file line number Diff line number Diff line change
Expand Up @@ -89,22 +89,22 @@ def __init__(self, trip_current: RangeLike) -> None:
[Power, Input],
)
self.pwr_out = self.Port(
VoltageSource(voltage_out=self.pwr_in.link().voltage, current_limits=RangeExpr()), # ignore voltage drop
VoltageSource(voltage=self.pwr_in.link().voltage, current_limits=RangeExpr()), # ignore voltage drop
[Output],
)

self.fuse = self.Block(
self.FUSE_TYPE(
trip_current=trip_current,
hold_current=(self.pwr_out.link().current_drawn.upper(), float("inf")),
hold_current=(self.pwr_out.link().current_draw.upper(), float("inf")),
voltage=self.pwr_in.link().voltage,
)
)
self.connect(self.pwr_in.net, self.fuse.a)
self.connect(self.pwr_out.net, self.fuse.b)

self.assign(self.pwr_in.voltage_limits, self.fuse.actual_voltage_rating) # TODO: eventually needs a ground ref
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw)
self.assign(self.pwr_out.current_limits, (0, self.fuse.actual_hold_current.lower()))

def connected(
Expand Down
8 changes: 4 additions & 4 deletions edg/abstract_parts/IdealIoController.py
Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ def generate(self) -> None:
for elt in self.get(self.dac.requested()):
aout = self.dac.append_elt(AnalogSource.from_supply(self.gnd, self.pwr), elt)
io_current_draw_builder = io_current_draw_builder + (
aout.link().current_drawn.lower().min(0),
aout.link().current_drawn.upper().max(0),
aout.link().current_draw.lower().min(0),
aout.link().current_draw.upper().max(0),
)

dio_model = DigitalBidir.from_supply(self.gnd, self.pwr, pullup_capable=True, pulldown_capable=True)
Expand All @@ -72,8 +72,8 @@ def generate(self) -> None:
for elt in self.get(self.gpio.requested()):
dio = self.gpio.append_elt(dio_model, elt)
io_current_draw_builder = io_current_draw_builder + (
dio.link().current_drawn.lower().min(0),
dio.link().current_drawn.upper().max(0),
dio.link().current_draw.lower().min(0),
dio.link().current_draw.upper().max(0),
)

self.spi.defined()
Expand Down
4 changes: 2 additions & 2 deletions edg/abstract_parts/Inductor.py
Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ def __init__(
self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Power, Input])
self.pwr_out = self.Port(
VoltageSource(
voltage_out=self.pwr_in.link().voltage,
voltage=self.pwr_in.link().voltage,
),
[Output],
)
Expand All @@ -202,7 +202,7 @@ def __init__(

self.connect(self.pwr_in.net, self.ind.a)
self.connect(self.pwr_out.net, self.ind.b)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw)

def connected(
self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optional[Port[VoltageLink]] = None
Expand Down
14 changes: 10 additions & 4 deletions edg/abstract_parts/IoController.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
import warnings
from itertools import chain
from typing import List, Dict, Tuple, Type, Optional, Any, Union, Callable, Mapping, Iterable
from typing_extensions import override
Expand Down Expand Up @@ -63,6 +64,11 @@ def __getattr__(self, item: str) -> Any:
from .IoControllerInterfaceMixins import IoControllerCan

self._can_mixin = self.with_mixin(IoControllerCan())
warnings.warn(
f"can is now a mixin, use .with_mixin(IoControllerCan()).can mixin instead",
DeprecationWarning,
stacklevel=2,
)
return self._can_mixin.can
else:
raise AttributeError(
Expand Down Expand Up @@ -230,17 +236,17 @@ def _instantiate_from(

if isinstance(io_port, DigitalBidir):
io_current_draw_builder = io_current_draw_builder + (
io_port.link().current_drawn.lower().min(0),
io_port.link().current_drawn.upper().max(0),
io_port.link().current_draw.lower().min(0),
io_port.link().current_draw.upper().max(0),
)
elif isinstance(io_port, AnalogSink):
pass # assumed no current draw into a sink
elif isinstance(io_port, TouchDriver):
pass # assumed no current draw
elif isinstance(io_port, AnalogSource):
io_current_draw_builder = io_current_draw_builder + (
io_port.link().current_drawn.lower().min(0),
io_port.link().current_drawn.upper().max(0),
io_port.link().current_draw.lower().min(0),
io_port.link().current_draw.upper().max(0),
)
# TODO: recurse into bundles, really needs a more unified way of handling current draw

Expand Down
8 changes: 4 additions & 4 deletions edg/abstract_parts/IoControllerInterfaceMixins.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@

from ..electronics_interfaces import *
from .IoController import BaseIoController, IoController
from ..util import deprecated_param_remap


class IoControllerSpiPeripheral(BlockInterfaceMixin[BaseIoController]):
Expand Down Expand Up @@ -145,9 +146,8 @@ def _generate_gnd_node(self) -> Ground:
self.gnd_model = self.Block(DummyGround())
return self.gnd_model.io

def _generate_pwr_node(
self, voltage_out: RangeLike, current_limits: RangeLike
) -> Union[VoltageSink, VoltageSource]:
@deprecated_param_remap(("voltage_out", "voltage"))
def _generate_pwr_node(self, voltage: RangeLike, current_limits: RangeLike) -> Union[VoltageSink, VoltageSource]:
"""Helper function that returns a power node, either directly taking the pwr port if available,
or generating an internal voltage node and optionally connecting it to pwr_out (if used).

Expand All @@ -159,7 +159,7 @@ def _generate_pwr_node(
else:
self.pwr_out_model = self.Block(
DummyVoltageSource(
voltage_out=voltage_out, # tolerance is a guess
voltage=voltage, # tolerance is a guess
current_limits=current_limits,
)
)
Expand Down
6 changes: 3 additions & 3 deletions edg/abstract_parts/IoControllerWrapper.py
Original file line number Diff line number Diff line change
Expand Up @@ -100,20 +100,20 @@ def recurse_port(port: Port, prefix: str) -> None:

def _remap_to_footprint_pinning(
self, pin_assigns: Dict[str, Tuple[Optional[str], Optional[str]]], pin_dict: Dict[str, Port]
) -> Dict[str, HasPassivePort]:
) -> Dict[str, Union[Passive, HasPassivePort]]:
"""Generates pinning that can be passed into a footprint, given the pin assign dict from _remap_pin_assigns_list
and pin dict from _generator_pin_dict.

This requires all pins to be assigned.

Internal utility.
"""
pinning: Dict[str, HasPassivePort] = {}
pinning: Dict[str, Union[Passive, HasPassivePort]] = {}

for name, assign in pin_assigns.items():
assert name in pin_dict
port = pin_dict[name]
if not isinstance(port, HasPassivePort):
if not isinstance(port, (Passive, HasPassivePort)):
continue # ignore non-leaf ports
assert assign[1] is not None, f"pin {name} missing pin number assignment"
pinning[assign[1]] = port
Expand Down
12 changes: 6 additions & 6 deletions edg/abstract_parts/Jumper.py
Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,10 @@ def contents(self) -> None:
class VoltageJumper(TypedJumper, Block):
def __init__(self) -> None:
super().__init__()
self.input = self.Port(VoltageSink(current_draw=RangeExpr(), reverse_voltage_out=RangeExpr()), [Input])
self.input = self.Port(VoltageSink(current_draw=RangeExpr(), reverse_voltage=RangeExpr()), [Input])
self.output = self.Port(
VoltageSource(
voltage_out=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_drawn
voltage=self.input.link().voltage, reverse_current_draw=self.input.link().reverse_current_draw
),
[Output],
)
Expand All @@ -45,8 +45,8 @@ def __init__(self) -> None:
def contents(self) -> None:
super().contents()
self.device = self.Block(Jumper())
self.assign(self.input.current_draw, self.output.link().current_drawn)
self.assign(self.input.reverse_voltage_out, self.output.link().reverse_voltage)
self.assign(self.input.current_draw, self.output.link().current_draw)
self.assign(self.input.reverse_voltage, self.output.link().reverse_voltage)
self.connect(self.input.net, self.device.a)
self.connect(self.output.net, self.device.b)

Expand All @@ -56,14 +56,14 @@ def __init__(self) -> None:
super().__init__()
self.input = self.Port(DigitalSink(current_draw=RangeExpr()), [Input])
self.output = self.Port(
DigitalSource(voltage_out=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds),
DigitalSource(voltage=self.input.link().voltage, output_thresholds=self.input.link().output_thresholds),
[Output],
)

@override
def contents(self) -> None:
super().contents()
self.device = self.Block(Jumper())
self.assign(self.input.current_draw, self.output.link().current_drawn) # for model purposes, treat as connected
self.assign(self.input.current_draw, self.output.link().current_draw) # for model purposes, treat as connected
self.connect(self.input.net, self.device.a)
self.connect(self.output.net, self.device.b)
10 changes: 5 additions & 5 deletions edg/abstract_parts/LinearRegulator.py
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ def contents(self) -> None:
super().contents()
effective_output_voltage = self.output_voltage.intersect((0, self.pwr_in.link().voltage.upper()))
self.gnd.init_from(Ground())
self.pwr_in.init_from(VoltageSink(current_draw=self.pwr_out.link().current_drawn))
self.pwr_out.init_from(VoltageSource(voltage_out=effective_output_voltage))
self.pwr_in.init_from(VoltageSink(current_draw=self.pwr_out.link().current_draw))
self.pwr_out.init_from(VoltageSource(voltage=effective_output_voltage))
self.reset.init_from(DigitalSink())


Expand All @@ -52,12 +52,12 @@ def __init__(self) -> None:
[Power, Input],
)
self.pwr_out = self.Port(
VoltageSource(voltage_out=self.RangeExpr(), current_limits=RangeExpr()), # parameters set by subtype
VoltageSource(voltage=self.RangeExpr(), current_limits=RangeExpr()), # parameters set by subtype
[Output],
)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn + self.actual_quiescent_current)
self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_draw + self.actual_quiescent_current)

self.require(
self.pwr_out.voltage_out.lower() + self.actual_dropout.upper() <= self.pwr_in.link().voltage.lower(),
self.pwr_out.voltage.lower() + self.actual_dropout.upper() <= self.pwr_in.link().voltage.lower(),
"excessive dropout",
)
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