[DO NOT MERGE][DRAFT] fix#50
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…Queue Large multimodal pixel_values tensors (100-200MB) were pickle-serialized into the broadcast payload on the engine (THPStorage_writeFileRaw) and deserialized on every local TP reader (THPStorage_readFileRaw), blocking the EngineCore step loop ~1s per large image with all GPUs idle. Add ShmTensorArena: a slotted shared-memory region (per-slot reader flags, same protocol as ShmRingBuffer). A Pickler.reducer_override diverts large contiguous CPU tensors into a free slot (single memcpy) and pickles only a (slot, nbytes, dtype, shape) stub; readers rebuild the tensor as a zero-copy torch.frombuffer view of the mapped slot. Slots are released lazily at the reader's next dequeue (worker loop is sequential, so the previous step's HtoD has completed). The writer never blocks: no free slot or oversize tensor falls back to the default in-band pickling. Env knobs: VLLM_SHM_TENSOR_ARENA (default on), _SLOTS (8), _SLOT_MB (256), _MIN_MB (8). Local readers only; disabled when remote readers exist. Unit test: 199MB bf16 roundtrip to 2 forked readers = 66.7ms enqueue (vs ~1275ms pickled), checksums exact, slot reuse + fallback verified. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The zero-copy tensor views the tmpfs mapping; without pinning, the HtoD pays first-touch page faults + pageable staging (~600-800ms observed for a 192MB image). Lazy one-time cudaHostRegister at first get_tensor makes every later HtoD a true DMA. Falls back gracefully when the process has no CUDA context. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Documents the multimodal engine->worker transport bottleneck (in-band pickle of large pixel_values tensors in MessageQueue.enqueue, per-rank deserialize, engine-loop head-of-line blocking) and the ShmTensorArena zero-copy design that removes it, including the pinning rationale, configuration knobs, validation results, and known limitations. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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