Fix CRC residue matching

[aca-logimentor]

Summary

• compare CRC check state against the computed residue instead of all-zero, so xorout-based CRCs can validate data plus transmitted CRC
• add synchronous init_i reloads for serial and parallel CRC engines, and keep match_o stable while dv_i is low
• reflect parallel input bits per byte for reflected CRCs on wide buses, add g_xor_out length checks, and allow CRC widths up to 64 bits
• make init/xor generic width mismatches fail elaboration in synthesis by assigning them directly to constrained constants
• cover serial flush_i behavior and document match_o, init_i, and flush_i semantics
• add an Unreleased changelog entry for the match_o compatibility change

Root Cause

The check path assumed that appending the CRC always drives the internal register to zero. That is only true when the appended CRC is the internal un-xored register value, or when xorout is zero. Standard transmitted CRC fields include xorout, so the final state is the algorithm residue instead.

Validation

• VUNIT_SIMULATOR=ghdl .\.venv\Scripts\python.exe sim\scripts\run.py --level fast --clean --output-path vunit_out
• Result: 142/142 passed