Issues

• [Formal finding VEX-RTL-019] medelegh is not implemented on an XLEN=32 hart with S-mode, so the upper half of the 64-bit medeleg is unreachable and a read traps

  SpinalHDL/VexRiscv#498 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-016] scause implements only 4 bits of Exception Code, but the architecture requires bits 4-0 so the register can hold 0-31

  SpinalHDL/VexRiscv#497 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-015] menvcfg and menvcfgh are not implemented on a hart with U-mode and S-mode, so reads of them raise illegal-instruction exceptions

  SpinalHDL/VexRiscv#496 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-014] sepc has no low-bit masking: sepc[0] is writable and reads back as one

  SpinalHDL/VexRiscv#495 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-011] mstatus.MPRV is not writable on a hart that implements U-mode

  SpinalHDL/VexRiscv#494 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-010] misa.Extensions reports B and G and omits I on a core that implements RV32I, and the E bit is not the complement of I

  SpinalHDL/VexRiscv#493 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-007] mtval is not written on an interrupt trap, so it retains the faulting address left by the previous exception instead of being set to zero

  SpinalHDL/VexRiscv#492 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-006] mcause has no reset value, so after reset it reads an undefined value instead of one indicating the cause of the reset

  SpinalHDL/VexRiscv#491 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-004] On an environment-call exception mtval is written with the ECALL instruction encoding instead of zero

  SpinalHDL/VexRiscv#490 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-003] mepc has no low-bit masking: mepc[0] is writable and reads back as one, and MRET then redirects the fetch to an unaligned address

  SpinalHDL/VexRiscv#489 · Filter by author StandardAsh opened on Sep 18, 2026

• [Formal finding VEX-RTL-002] MRET sets mstatus.MPP to 00 (U-mode) on a hart that implements only M-mode, leaving an unsupported privilege encoding architecturally readable

  SpinalHDL/VexRiscv#488 · Filter by author StandardAsh opened on Sep 18, 2026

• MMU plugin allows supervisor execution of code in user pages when status.SUM is 1

  SpinalHDL/VexRiscv#487 · Filter by author MichaelBell opened on Sep 17, 2026
  4

• mcounteren (0x306) and scounteren (0x106) are not implemented on harts with U-mode / S-mode

  SpinalHDL/VexRiscv#486 · Filter by author StandardAsh opened on Sep 12, 2026

• mstatus.TVM / TW / TSR are hardwired to zero on configurations with S-mode and U-mode

  SpinalHDL/VexRiscv#485 · Filter by author StandardAsh opened on Sep 12, 2026

• sstatus exposes mstatus.MPRV at bit 17 and lets S-mode write it

  SpinalHDL/VexRiscv#484 · Filter by author StandardAsh opened on Sep 12, 2026

• Critical Failure on Anlogic TD based FPGA with Murax

  SpinalHDL/VexRiscv#482 · Filter by author briansune opened on Aug 28, 2026

• Question about EmbeddedRiscvJtag, DebugPlugin, and OpenOCD debugging via Xilinx BSCANE2

  SpinalHDL/VexRiscv#479 · Filter by author Usutatsu opened on Aug 5, 2026

• Questions: APB3 ArrayBuffer via Apb3Decoder & CPU M plugin

  SpinalHDL/VexRiscv#477 · Filter by author briansune opened on Jun 1, 2026

• Question and puzzling about prebuilt Hex under resource folder for Murax demo

  SpinalHDL/VexRiscv#476 · Filter by author briansune opened on May 23, 2026
  2

• share Risc-V knowledge for Future Digital Civilization Technology

  SpinalHDL/VexRiscv#474 · Filter by author fatalfeel opened on May 3, 2026

• Assertion with configuration

  SpinalHDL/VexRiscv#473 · Filter by author RossComputerGuy opened on Mar 8, 2026
  1

• How do I add VexRiscv as a dependency in a mill project

  SpinalHDL/VexRiscv#472 · Filter by author parthkalgaonkar opened on Mar 1, 2026
  3

• What is the cycle latency of VexRiscv FPU double‑precision add (FADD.D), and how can I derive it from the RTL/config?

  SpinalHDL/VexRiscv#469 · Filter by author Usutatsu opened on Jan 22, 2026
  1

• [Bug] CSR writes to cycle/instret do not raise illegal-instruction

  SpinalHDL/VexRiscv#465 · Filter by author canxin121 opened on Nov 24, 2025
  1

• [Bug] VexRiscv FSGNJX.D Sign Bit Wrong

  SpinalHDL/VexRiscv#464 · Filter by author canxin121 opened on Nov 24, 2025
  1