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Add FPGA registers and IRQ support for querying 10G link state
latentpinkLATENTPINK 14+1 port prototype switchLATENTPINK 14+1 port prototype switchStatus: Open.#4 In azonenberg/latentpacket;Add IRQ support for baseT link status change to avoid nonstop polling
latentpinkLATENTPINK 14+1 port prototype switchLATENTPINK 14+1 port prototype switchStatus: Open.#3 In azonenberg/latentpacket;- Status: Open.#2 In azonenberg/latentpacket;
- Status: Open.#1 In azonenberg/latentpacket;