A small, heavily-commented SystemVerilog project for the Terasic DE1-SoC (Intel/Altera Cyclone V, 5CSEMA5F31C6). It writes a test pattern into a block RAM, reads it back one word every half-second, and displays the result on the red LEDs.
The design itself is deliberately trivial. The point is everything around it: inferring a hard memory block instead of accidentally building it out of flip-flops, generating slow events without generating a slow clock, and — the real lesson — writing a state machine that correctly accounts for a memory's read latency.
This is a learning resource. The source files carry far more comment than code, and are meant to be read top-to-bottom in the order given below.
Status: builds clean in Quartus Prime 25.1 Lite, both testbenches pass in Questa. 39 ALMs, 1 M10K block, +16.1 ns setup slack at 50 MHz.
Each file is a self-contained lesson. Read them in this sequence:
- rtl/tick_gen.sv — why you never build a divided clock on an FPGA; one clock, many enables.
- rtl/single_port_ram.sv — the exact code shape Quartus pattern-matches to infer a hard M10K block, and the one-cycle read latency.
- rtl/sweeper_fsm.sv — three-block FSM, and the heart of the project: how not to drop the last word of a read burst.
- rtl/bram_sweeper_top.sv — structural top level; what a port physically is, and converting reset polarity once at the boundary.
- m10k_ram.sdc — timing constraints, and why an unconstrained design "fails timing" even when it's fast.
- tb/tb_single_port_ram.sv → tb/tb_bram_sweeper.sv — unit test first, then the full system with a scoreboard.
- Quartus Prime Lite Edition 25.1std.0 Build 1129
- Questa Altera Starter FPGA Edition 2025.2
- Terasic DE1-SoC, Cyclone V
5CSEMA5F31C6