feat(verilog): index Verilog/SystemVerilog, resolve port bindings, signal access and build profiles - #1875
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danusha2345 wants to merge 8 commits into
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feat(verilog): index Verilog/SystemVerilog, resolve port bindings, signal access and build profiles#1875danusha2345 wants to merge 8 commits into
danusha2345 wants to merge 8 commits into
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