[TLE][BACKEND] Add AMD tile and cumsum lowering

[zihaomu]

What

• Add AMD LLVM lowering for tle.extract_tile, tle.insert_tile, and tle.exclusive_cumsum.
• Register AMD shared-memory scratch allocation for the three operations.
• Select thread-id, barrier, and shuffle lowering through target capabilities instead of backend identity.
• Keep backend-owned TargetInfoBase copies source-compatible with the shared capability API.
• Report residual unsupported TLE operations with their names and AMD target architecture.

Why

The shared TLE lowering previously emitted NVIDIA-specific thread-id, barrier, and shuffle operations unless the target identified as HCU. AMD therefore could not lower these portable tile operations even though its target interface already provides the required primitives.

This change lets the AMD backend reuse the shared lowering while preserving existing behavior for NVIDIA, HCU, Iluvatar, Metax, and MThreads.

Testing

• gfx1201 extract/insert/cumsum tests: 13 passed, 4 skipped
  • Skips are NVIDIA PTX, HCU ISA, and the follow-up AMD local-pointer lowering cases.
• AMD residual-op diagnostic tests: 2 passed
• AMD triton-opt + FileCheck regression for extract_tile, insert_tile, and exclusive_cumsum: passed
• Ninja build and libtriton.so link: passed
• Ruff 0.9.1, YAPF 0.43.0, clang-format 19.1.6, and git diff --check: passed
• merge-tree against current upstream main: conflict-free

Cross-backend validation

An HCU-equivalent wheel build compiled the changed TargetInfo.cpp and TritonGPUToLLVM.cpp. It later stopped in the unchanged TargetUtils.cpp because the local LLVM package does not contain HCU-specific GPU enums (GK_GFX928, GK_GFX936, and related targets). The upstream HCU/Iluvatar/Metax/MThreads CI jobs remain the final cross-backend gate.