All pull requests

Pull requests

• [AXI4] Add cdc op

  #11147·TaoBi22 opened Sep 21, 2026·2/2·

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  1

• [AXI4] Add cut op

  #11146·TaoBi22 opened Sep 21, 2026·1/2·

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  1

• [MooreToCore][LLHD] Support dynamic part-select writes to packed structs

  #11142·liW-J opened Sep 20, 2026·

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  1

• [ExportVerilog] Change hw.union padding to match bitcast layout

  ExportVerilog
  #11135·fzi-hielscher opened Sep 16, 2026·

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  10

• [ImportVerilog] Support string casts to packed arrays

  #11134·dagronlund opened Sep 16, 2026·

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• [ImportVerilog] Support concurrent cover properties and sequences

  #11132·dagronlund opened Sep 16, 2026·

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  1

• [ImportVerilog] Support assignment patterns as assignment destinations

  #11131·dagronlund opened Sep 16, 2026·

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  5

• [ImportVerilog] Resolve hierarchical outputs from expanded interfaces

  #11130·dagronlund opened Sep 16, 2026·

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  10

• [ImportVerilog] Support connected interface-array ports

  #11129·dagronlund opened Sep 16, 2026·

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• [AXI4ToHW] Lower AXI4 ports

  #11125·TaoBi22 opened Sep 16, 2026·

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  2

• [FIRRTL] Bounce non-connect users of dropped zero-width instance ports

  #11118·arcusbuilds opened Sep 15, 2026·

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  1

• [Handshake] Fix argument indexing in LowerExtmemToHW with several memories

  #11112·kevinyuan opened Sep 12, 2026·

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  5

• [ImportVerilog] Support fixed-size aggregates in streaming operators

  #11110·SathsaraGeeth opened Sep 12, 2026·

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  6

• [Seq][RegOfVecToMem] Recognize masked memory writes

  #11106·SawyDust1228 opened Sep 11, 2026·

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• [HandshakeRunner] Fix memref CLI arguments and add missing integer arith ops

  #11104·kevinyuan opened Sep 11, 2026·

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• Bump LLVM

  #11096·uenoku opened Sep 10, 2026·

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  2

• [Calyx] Reject invoke ops passing ref cells to local instances

  #11095·Jimmy-Hu opened Sep 10, 2026·

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  8

• [HandshakeToHW] Reject non-integer constants instead of crashing

  #11094·kevinyuan opened Sep 9, 2026·

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• [ImportVerilog] Add MOS switch primitive support

  #11093·mafeguimaraes opened Sep 9, 2026·

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  40

• [FIRRTL] Lower SizeOfIntrinsicOp when optimizations are disabled

  #11090·AlexanderPortland opened Sep 9, 2026·

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• [ImportVerilog] Add support for three-stage buffers and inverters

  #11089·joaovam opened Sep 8, 2026·

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  29

• [FIRRTL] Add preserve-modules option for DropNamePass

  #11086·FPC5719 opened Sep 8, 2026·

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• [MooreToCore] Support DPI open array conversion lowering (#11025)

  #11084·amanmaurya92 opened Sep 5, 2026·

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  7

• [LLHD] Preserve explicit register initializers through Deseq

  #11081·5iri opened Sep 5, 2026·

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  4

• [ProbeToSV] Lower probe.send/probe.read to SV

  #11077·nanjo712 opened Sep 3, 2026·2/2·

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  39