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[tlib] riscv: mcountinhibit does not stop mcycle/minstret immediately

Status: Open.

#910 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: CSRRW/CSRRWI with rd=x0 still read the CSR and trap on write-only CSRs

Status: Open.

#909 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: sfence.vma executed in U-mode does not raise illegal-instruction

Status: Open.

#908 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: U-mode counter access ignores mcounteren when scounteren is set

Status: Open.

#907 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: mepc bit 0 is not cleared on write

Status: Open.

#906 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: sepc does not clear bit 0 on write

Status: Open.

#905 In renode/renode;

· whensun opened on May 1, 2026

[tlib] riscv: menvcfg accepts unsupported bits and reads back all ones

Status: Open.

#904 In renode/renode;

· whensun opened on May 1, 2026

[tlib] RISC-V vector CSRs are not masked, mirrored, or gated through mstatus.VS correctly

Status: Open.

#903 In renode/renode;

· whensun opened on May 1, 2026

ZephyrRTOS + Max33652 GPIO2 output not supported

Status: Open.

#902 In renode/renode;

· skemo12 opened on Apr 29, 2026

Support for nrf5340 SoC

Status: Open.

#900 In renode/renode;

· isimeonov14 opened on Apr 16, 2026

STM32_Timer TRGO and master/slave-mode features

Status: Open.

#898 In renode/renode;

· jaguilar opened on Apr 8, 2026

ARMv8.1-M CSET instruction not working as expected

Status: Open.

#897 In renode/renode;

· debuti opened on Apr 8, 2026