Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -126,11 +126,11 @@ jobs:
cargo install svd2rust --path .

# Install the MSRV toolchain
- uses: dtolnay/rust-toolchain@1.81.0
- uses: dtolnay/rust-toolchain@1.85.0
- name: Run reression tool with MSRV
# The MSRV only applies to the generated crate. The regress tool should still be run with
# stable.
run: cargo +stable regress tests --toolchain 1.81.0 -m Nordic -- --strict --atomics
run: cargo +stable regress tests --toolchain 1.85.0 -m Nordic -- --strict --atomics

ci-docs-clippy:
runs-on: ubuntu-latest
Expand Down
1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
- Add AVR specific settings (`avr_config`) to the `--settings` file, declaring
which registers are CCP protected; `Protected` trait implementations are
generated from it
- Add `Reg::prepare`.

## [v0.37.1] - 2025-10-17

Expand Down
4 changes: 2 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@ This project is developed and maintained by the [Tools team][team].

## Minimum Supported Rust Version (MSRV)

The **generated code** is guaranteed to compile on stable Rust 1.81.0 and up.
The **generated code** is guaranteed to compile on stable Rust 1.85.0 and up.

If you encounter compilation errors on any stable version newer than 1.81.0, please open an issue.
If you encounter compilation errors on any stable version newer than 1.85.0, please open an issue.

# Testing Locally

Expand Down
14 changes: 14 additions & 0 deletions src/generate/generic_reg_vcell.rs
Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,20 @@ impl<REG: Resettable + Writable> Reg<REG> {
value
}

/// Prepare bits for delayed write to register.
#[inline(always)]
pub fn prepare<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits
}

/// Writes bits to a `Writable` register and produce a value.
///
/// You can write raw bits into a register:
Expand Down
Loading