Harden I2C and SPI hardware edge cases

[floitsch]

Stacked on #3161. The required ESP-IDF patch head is already on master.

This follow-up closes the remaining review and hardware-test gaps for the asynchronous I2C/SPI stack:

• Adds deterministic retryable-OOM cleanup tests for target and controller allocation paths.
• Tests I2C clock stretching, a bus held low before START, FIFO boundaries, exact overflow accounting, abort, and reuse.
• Adds the i2c.Target --default-response option: a bounded fallback response used whenever no ordinary transmit data is ready. Ordinary write data takes over at a read-transaction boundary, and the default is restored automatically after that stream drains.
• Covers the full request protocol on paired boards: repeated not-ready reads, controller request, queued ready response, and automatic return to not-ready.
• Expands SPI target and buffer-target coverage across modes 0-3, single/full-duplex direction changes, bit order, DMA/non-DMA, queue overflow, abort/close, and non-byte-aligned CS termination.
• Measures every supported CS setup/hold value with independent RMT probes and verifies the clock count.
• Adds CONFIG_TOIT_ENABLE_I2C_TARGET and CONFIG_TOIT_ENABLE_SPI_TARGET; disabling either compiles its implementation and dependencies out, while both remain enabled in the default envelope.
• Keeps CONFIG_SPI_MASTER_ISR_IN_IRAM=y on classic ESP32 while retaining both targets.
• Hardens staged construction, cancellation, cleanup, teardown ordering, queue allocation, and target response arbitration.
• Marks one-data-line controller buses as half-duplex and rejects the unrepresentable classic-ESP32 hold value 16.
• Adds a tracking document with the coverage inventory and hardware evidence.

The original ESP32 ACKs an empty target read but returns undefined FIFO contents; an observed eight-byte read was b5 ff ff ff ff ff ff ff. The configured default makes this case deterministic without clock stretching.

Hardware verification using paired boards:

• ESP32: complete I2C/SPI selection 15/15 after setup and 12/12 immediately without setup.
• ESP32-S3: complete I2C/SPI selection 15/15 after setup and 12/12 immediately without setup.
• Focused default-response I2C tests pass on both variants, including short dynamic responses and transitions back to the fallback response.
• Changed Toit sources pass analysis with warnings treated as errors; host, target-disabled, ESP32, and ESP32-S3 builds pass.
• Native ESP-IDF I2C/SPI builds pass with the relevant IRAM-safe options enabled.