Bump FireSim and add MimicTurbo GT and Alveo V80 sample recipes and bitstreams

[raghav-g13]

Add single-core Rocket FireSim build recipes and pre-built bitstream hwdb entries for two boards added in FireSim: the Corigine MimicTurbo GT (VU19P, firesim/firesim#1890) and the Xilinx Alveo V80 (Versal, firesim/firesim#1892).

• corigine_mimicturbo_gt_firesim_rocket_singlecore_4GB_no_nic: FireSimRocket4GiBDRAMConfig + BaseCorigineMimicTurboGTConfig, 60 MHz, TIMING. The board has 8 GiB of host DRAM, so the recipe uses the 4 GiB variant rather than the 16 GiB default (like the VCU118 recipe). Bitstream: https://bitstreams.ucb.bar/corigine_mimicturbo_gt/corigine_mimicturbo_gt_firesim_rocket_singlecore_4GB_no_nic.tar.gz.
• xilinx_alveo_v80_firesim_rocket_singlecore_no_nic: FireSimRocketConfig + BaseXilinxAlveoV80Config, 10 MHz, RUNTIME_OPTIMIZED. It meets setup and hold timing with margin, so it doubles as the known-good image that the FireSim V80 setup guide writes to flash. Bitstream: https://bitstreams.ucb.bar/xilinx_alveo_v80/xilinx_alveo_v80_firesim_rocket_singlecore_no_nic.tar.gz.

FireSim bump: sims/firesim moves from 2004c7d36 (the docs-update merge) to b83185442, current FireSim main. That brings in:

• On-prem infra fixes and improvements firesim/firesim#1889: on-premises FPGA infrastructure fixes (single-session JTAG programming and enumeration, XDMA loading via modprobe, the RUNTIME_OPTIMIZED build strategy, 8 GB FASED configs, and more);
• Add FireSim port for Corigine MimicTurbo GT (VU19P) firesim/firesim#1890: the Corigine MimicTurbo GT platform;
• Add Xilinx Alveo V80 (Versal) platform support firesim/firesim#1892: the Xilinx Alveo V80 platform;
• Fix cryptography, paramiko deps versioning firesim/firesim#1888: the Fab Classic / Paramiko install fix in FireSim's setup scripts.

Testing:

• MimicTurbo GT: this recipe was built, and it booted Buildroot Linux on a MimicTurbo GT from the FireSim branch.
• Alveo V80: this recipe was built meeting timing. The PDI was written to the V80's flash, and firesim enumeratefpgas, infrasetup and runworkload booted Buildroot Linux on the V80, on a machine that also hosts a MimicTurbo GT.

Related PRs / Issues:

• MimicTurbo GT platform: Add FireSim port for Corigine MimicTurbo GT (VU19P) firesim/firesim#1890 (merged)
• Alveo V80 platform: Add Xilinx Alveo V80 (Versal) platform support firesim/firesim#1892 (merged)
• Also included in the FireSim bump: On-prem infra fixes and improvements firesim/firesim#1889 and Fix cryptography, paramiko deps versioning firesim/firesim#1888

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other: FireSim submodule bump, plus sample build recipe and hwdb configs. The bump changes FireSim-generated simulator RTL for all targets: LoadMem bursts are split at 4 KB boundaries (Add Xilinx Alveo V80 (Versal) platform support firesim/firesim#1892). Target RTL is unchanged.

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file? (N/A)
• (If applicable) Did you add documentation for the feature? (The getting-started guides are in the FireSim PRs.)
• (If applicable) Did you add a test demonstrating the PR? (N/A: tested manually on hardware, see above)
• (If applicable) Did you mark the PR as Please Backport? (N/A)

CI Help:
Add the following labels to modify the CI for a set of features.
Generally, a label added only affect subsequent changes to the PR (i.e. new commits, force pushing, closing/reopening).
See ci:* for full list of labels:

• ci:fpga-deploy - Run FPGA-based E2E testing
• ci:local-fpga-buildbitstream-deploy - Build local FPGA bitstreams for platforms that are released
• ci:disable - Disable CI

[mergify]

Queued — the merge queue status continues in this comment ↓.

[mergify]

Merge Queue Status

• ✅ Entered queue — 2026-10-05 18:33 UTC · Rule: default · triggered by @raghav-g13 with the merge queue checkbox
• ✅ Checks skipped · PR is already up-to-date
• ✅ Merged — 2026-10-05 18:33 UTC · at bfa5699fe9c7b0ffbff7bd972e362bf507f8bf21

This pull request spent 15 seconds in the queue, including 2 seconds running CI.

Required conditions to merge

• github-review-approved [🛡 GitHub branch protection]
  • Bump FireSim and add MimicTurbo GT and Alveo V80 sample recipes and bitstreams #2385