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Add SWD debug transport to the SMP cluster - #483
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Wire DebugTransportModuleSwd into VexRiscvSmpCluster as an alternative to the JTAG DTM (--swd, mutually exclusive with --jtag-tap, requires privilegedDebug) and expose SWCLK/SWDIO as LiteX black-box ports. Add SpinalSim coverage for the SWD wire protocol, DP, and DM, plus a shared host bitbang driver.
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This was referenced Sep 23, 2026
Dolu1990
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Sep 27, 2026
EmbeddedRiscvJtag puts the official RISC-V debug module and its transport inside the CPU. Its transports were JTAG only (TAP, tunneled TAP or instruction port), while the SMP cluster got SWD in #483 / #499. Add withSwd, which uses the existing DebugTransportModuleSwd (SWCLK/SWDIO, a RISC-V debug spec Ch. 6 custom DTM) in place of the JTAG transport and exposes a "swd" port. Only one transport can be used at a time, so withTap and withTunneling are ignored when withSwd is set. The GenFullWithOfficialRiscvDebug and Briey netlists, the two users of the plugin, are identical to dev.
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Wire DebugTransportModuleSwd into VexRiscvSmpCluster as an alternative to the JTAG DTM (--swd, mutually exclusive with --jtag-tap, requires privilegedDebug) and expose SWCLK/SWDIO as LiteX black-box ports.
Add SpinalSim coverage for the SWD wire protocol, DP, and DM, plus a shared host bitbang driver.