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Follow the SWD library split in SpinalHDL - #499
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SpinalHDL moved the SWD wire side (Swd bundle, SwdPhy, SwdDp) into spinal.lib.com.swd, and DebugTransportModuleSwd.io.swd is now slave(Swd()) with swdio as a TriState. The SMP cluster maps swdio.read/write/writeEnable onto the same pinned top-level names as before (debugPort_swdio_i/o/oe), so the LiteX black-box port map is unchanged and the generated netlist is identical up to internal port renames. The SWD PHY, DP and DTM suites and their sim driver never depended on VexRiscv; they now live in SpinalHDL's tester next to the code they test. Requires the matching SpinalHDL change.
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Dolu1990
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Sep 27, 2026
EmbeddedRiscvJtag puts the official RISC-V debug module and its transport inside the CPU. Its transports were JTAG only (TAP, tunneled TAP or instruction port), while the SMP cluster got SWD in #483 / #499. Add withSwd, which uses the existing DebugTransportModuleSwd (SWCLK/SWDIO, a RISC-V debug spec Ch. 6 custom DTM) in place of the JTAG transport and exposes a "swd" port. Only one transport can be used at a time, so withTap and withTunneling are ignored when withSwd is set. The GenFullWithOfficialRiscvDebug and Briey netlists, the two users of the plugin, are identical to dev.
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SpinalHDL moved the SWD wire side (Swd bundle, SwdPhy, SwdDp) into spinal.lib.com.swd, and DebugTransportModuleSwd.io.swd is now slave(Swd()) with swdio as a TriState.
The SMP cluster maps swdio.read/write/writeEnable onto the same pinned top-level names as before (debugPort_swdio_i/o/oe), so the LiteX black-box port map is unchanged and the generated netlist is identical up to internal port renames.
The SWD PHY, DP and DTM suites and their sim driver never depended on VexRiscv; they now live in SpinalHDL's tester next to the code they test.
Requires the matching SpinalHDL/1966.