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Merged
Dolu1990 merged 1 commit into from
Sep 19, 2026
Merged

Follow the SWD library split in SpinalHDL #499

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14 changes: 7 additions & 7 deletions src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -172,14 +172,14 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
debugCd = ClockDomain.current
)
dm.io.ctrl <> transport.io.bus
// Per-signal toIo: io.swd is an anonymous nested Bundle, so cloneOf (and therefore
// whole-bundle toIo) fails on it. Names are pinned explicitly because the LiteX
// black-box port map in vexriscv_smp/core.py depends on them.
// Per-signal toIo rather than transport.io.swd.toIo: the names are pinned because the
// LiteX black-box port map in vexriscv_smp/core.py depends on them (i/o/oe, not the
// TriState read/write/writeEnable of spinal.lib.com.swd.Swd).
val debugPort = Handle(new Area {
val swclk = transport.io.swd.swclk .toIo.setName("debugPort_swclk")
val swdio_i = transport.io.swd.swdio.i .toIo.setName("debugPort_swdio_i")
val swdio_o = transport.io.swd.swdio.o .toIo.setName("debugPort_swdio_o")
val swdio_oe = transport.io.swd.swdio.oe .toIo.setName("debugPort_swdio_oe")
val swclk = transport.io.swd.swclk .toIo.setName("debugPort_swclk")
val swdio_i = transport.io.swd.swdio.read .toIo.setName("debugPort_swdio_i")
val swdio_o = transport.io.swd.swdio.write .toIo.setName("debugPort_swdio_o")
val swdio_oe = transport.io.swd.swdio.writeEnable .toIo.setName("debugPort_swdio_oe")
})
}
})
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196 changes: 0 additions & 196 deletions src/test/scala/vexriscv/DebugSwdDmTest.scala
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166 changes: 0 additions & 166 deletions src/test/scala/vexriscv/DebugSwdDpTest.scala
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